Abstract: In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.

Abstract: A method and system of designing an electronic circuit includes dividing a chip area of a design into a plurality of bins, identifying a candidate bin in the plurality of bins, and performing an area reduction on the candidate bin.

Abstract: In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.

Abstract: A method and system of designing an electronic circuit includes dividing a chip area of a design into a plurality of bins, identifying a candidate bin in the plurality of bins, and performing an area reduction on the candidate bin.

Abstract: A method and system of designing an electronic circuit includes dividing a chip area of a design into a plurality of bins, identifying a candidate bin in the plurality of bins, and performing an area reduction on the candidate bin.

Abstract: Computationally efficient methods and systems for optimizing an integrated circuit (IC) design by targeting only a limited subsection of buffer trees in the buffer system for optimization are provided. By making intelligent decisions about which buffer trees to optimize, greater gains in design efficiency (e.g., as measured by reduced delays and/or wire length) may be realized at greatly reduced computational times when compared to conventional techniques that attempt to optimize each buffer tree.

Abstract: An apparatus, program product and method use a congestion relief algorithm in connection with automated buffer insertion to relieve potential congestion during post-layout interconnect routing. The congestion relief algorithm is utilized to manipulate a plurality of L-shaped spans defined in a routing tree, and is configured to apply the congestion relief algorithm to at least a first L-shaped span among the plurality of L-shaped spans by rerouting the first L-shaped span at least partially within a rectangular area bounded by the first L-shaped span.

Abstract: An apparatus, program product and method use a congestion relief algorithm in connection with automated buffer insertion to relieve potential congestion during post-layout interconnect routing. The congestion relief algorithm is utilized to manipulate a plurality of L-shaped spans defined in a routing tree, and is configured to apply the congestion relief algorithm to at least a first L-shaped span among the plurality of L-shaped spans by rerouting the first L-shaped span at least partially within a rectangular area bounded by the first L-shaped span.

Abstract: An apparatus, program product and method utilize an interactive request server program to interface a plurality of client computers with a timing analysis program. The interactive request server program receives client requests from the plurality of client computers over a network, and, in response to each client request, accesses the timing analysis program to retrieve timing data based upon such client request and thereafter forwards the timing data to the client computer making such request. The interactive request server program may optionally be implemented using a web server program and an application server program, with the web server program interfacing with the client computers via an Internet-type interface, and the application server program interfacing with the timing analysis program using a programmatic interface supported by the timing analysis program.

Abstract: Automatic generation of post-layout optimization circuitry allows a computer system running an integrated circuit design tool to automatically compensate for timing errors by synthesizing circuit elements to bring the timing within specified timing constraints. A new circuit element is assigned a location without determining an allowable physical location on the integrated circuit, and all timing calculations are based on the assigned location. Then, once the timing constraints have been met by one or more new circuit elements, an incremental layout is performed to find physical locations for the new circuit elements, using the assigned locations as initial targets. By using assigned locations during timing calculations and later determining valid physical locations, many different circuit configurations may be evaluated in a short period of time, with only the best ones going through the more time-consuming step of layout and routing.

Abstract: A simple system and method is disclosed that provides for the identification and removal of unnecessary buffers in a logic circuit. A special pseudo-buffer is added to the library and identified as a buffer cell with zero area. In addition, a feedthrough delay rule is associated with the pseudo-buffer such that it is treated by a timing system as a wire with no delay through which all electrical properties pass. An existing repowering function will then consider the pseudo-buffer as a replacement choice when attempting to select an optimal power level. If the pseudo buffer is chosen, it can be easily removed from the circuit at some time thereafter.

Abstract: A system for identifying and bounding the regions of a digital electronic logic design model that are affected by design revisions. The system is useful for improving the efficiency of incremental logic synthesis systems and includes procedures for recording the signals directly affected by user revision operations and for marking signals in the logic to identify those indirectly affected. A smart editor capable of parsing the formal register transfer language (RTL) in which the logic design is described is included in the system.