Patents by Inventor Anthony DeSantis

Anthony DeSantis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230270732
    Abstract: CCR2 is involved in the regulation of normal cardiovascular function and during the cardiovascular stress response to hemorrhagic shock and fluid resuscitation. Disclosed herein are methods of using CCR2 inhibitors to reduce fluid requirements and to prevent death from hemodynamic decompensation during resuscitation.
    Type: Application
    Filed: February 28, 2023
    Publication date: August 31, 2023
    Inventors: Matthias MAJETSCHAK, Anthony DESANTIS, Xianlong GAO
  • Patent number: 11676993
    Abstract: In one example an electronic device includes a first resistor and a second resistor. The first resistor includes a first resistive layer located over a substrate, the first resistive layer having a first sheet resistance. The second resistor includes a first portion of a second resistive layer located over the substrate, the second resistive layer having a second sheet resistance different from the first sheet resistance. The first resistive layer is located between the substrate and a second noncontiguous portion of the second resistive layer.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: June 13, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Christoph Andreas Othmar Dirnecker, Wolfgang Schwartz, Doug Weiser, Joel Martin Halbert, Joseph Anthony DeSantis, Karsten Jens Spinger
  • Publication number: 20200403061
    Abstract: In one example an electronic device includes a first resistor and a second resistor. The first resistor includes a first resistive layer located over a substrate, the first resistive layer having a first sheet resistance. The second resistor includes a first portion of a second resistive layer located over the substrate, the second resistive layer having a second sheet resistance different from the first sheet resistance. The first resistive layer is located between the substrate and a second noncontiguous portion of the second resistive layer.
    Type: Application
    Filed: September 8, 2020
    Publication date: December 24, 2020
    Inventors: Christoph Andreas Othmar Dirnecker, Wolfgang Schwartz, Doug Weiser, Joel Martin Halbert, Joseph Anthony DeSantis, Karsten Jens Spinger
  • Patent number: 10770538
    Abstract: A method of forming an electronic device includes forming an opening through a dielectric layer located over a first resistive layer, the first resistive layer having a first sheet resistance. A second resistive layer is deposited over the dielectric layer and into the opening. The second resistive layer has a second sheet resistance different from the first sheet resistance. A portion of the second resistive layer is removed, thereby forming first and second noncontiguous portions of the second resistive layer, wherein the second portion of the second resistive layer contacts the first resistive layer.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: September 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Christoph Andreas Othmar Dirnecker, Wolfgang Schwartz, Doug Weiser, Joel Martin Halbert, Joseph Anthony DeSantis, Karsten Jens Spinger
  • Publication number: 20190229419
    Abstract: An antenna apparatus for mounting on a non-conductive chassis with a printed circuit board includes a folded metal antenna element having an integral folded metal balun, wherein the balun is connected to the folded metal antenna, and metal end portions on the folded metal balun connect with conductive pads on a printed circuit board. The pads directly connect to RF circuitry on the printed circuit board such that an electrical connection between the metal end portions of the folded metal balun and the RF circuitry is made without an RF cable or separate connector.
    Type: Application
    Filed: April 7, 2017
    Publication date: July 25, 2019
    Inventors: William T Murphy, John M McMillan, Anthony Desantis
  • Publication number: 20180261664
    Abstract: An electronic device includes a first resistor and a second resistor. The first resistor includes a first resistive layer located over a substrate and having a first sheet resistance. The second resistor includes a first portion of a second resistive layer located over the substrate and having a second sheet resistance that is different from the first sheet resistance. The first resistive layer is located between the substrate and a second noncontiguous portion of the second resistive layer.
    Type: Application
    Filed: May 10, 2018
    Publication date: September 13, 2018
    Inventors: Christoph Andreas Othmar Dirnecker, Wolfgang Schwartz, Doug Weiser, Joel Martin Halbert, Joseph Anthony DeSantis, Karsten Jens Spinger
  • Patent number: 9991329
    Abstract: An integrated circuit includes a higher sheet resistance resistor and a lower sheet resistance resistor, disposed in a same level of dielectric layers of the integrated circuit. The higher sheet resistor has a body region and head regions in a higher sheet resistance layer. The lower sheet resistor has a body region and head regions in a lower sheet resistance layer, which is thicker than the higher sheet layer. The higher sheet resistor has an upper head layer contacting the higher sheet layer at each head region of the higher sheet layer. Each upper head layer has a same composition and thickness as the lower sheet layer of the lower sheet resistor. The lower sheet resistor is free of head layers over the lower sheet resistance layer.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: June 5, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Christoph Andreas Othmar Dirnecker, Wolfgang Schwartz, Doug Weiser, Joel Martin Halbert, Joseph Anthony DeSantis, Karsten Jens Spinger
  • Publication number: 20180019297
    Abstract: An integrated circuit includes a higher sheet resistance resistor and a lower sheet resistance resistor, disposed in a same level of dielectric layers of the integrated circuit. The higher sheet resistor has a body region and head regions in a higher sheet resistance layer. The lower sheet resistor has a body region and head regions in a lower sheet resistance layer, which is thicker than the higher sheet layer. The higher sheet resistor has an upper head layer contacting the higher sheet layer at each head region of the higher sheet layer. Each upper head layer has a same composition and thickness as the lower sheet layer of the lower sheet resistor. The lower sheet resistor is free of head layers over the lower sheet resistance layer.
    Type: Application
    Filed: July 13, 2016
    Publication date: January 18, 2018
    Inventors: Christoph Andreas Othmar Dirnecker, Wolfgang Schwartz, Doug Weiser, Joel Martin Halbert, Joseph Anthony DeSantis, Karsten Jens Spinger
  • Publication number: 20140193103
    Abstract: A drawstring bag with lockable strap using a combination lockable buckle and an internal compartment that is provided with a combination lockable zipper. This bag incorporates a desirably designed bag with the safety of a built-in combination lockable strap and buckle which allows the user to secure it to another object. Additionally, the internal compartment is accessed via a combination lockable zipper. Both locks have built in, easy to remember, codes.
    Type: Application
    Filed: January 7, 2014
    Publication date: July 10, 2014
    Applicant: Des-La Corporation
    Inventor: Anthony DeSanti
  • Patent number: 6992844
    Abstract: A system and method of forming a hermetic seal between a lens or window and a lid, which minimizes bending moments, and therefore, bifringance on the window or lens is disclosed. This is accomplished by use of a transition member, specific geometries, and selection of the coefficient of thermal expansion of the materials to insure that the solder joint is in compression on cool down and solder strains are maintained within acceptable limits. The transition member may be soldered or welded to lid or integral through machining.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: January 31, 2006
    Assignee: Special Hermetic Products, Inc.
    Inventors: John A. Pollock, Anthony DeSantis
  • Patent number: 6899545
    Abstract: A coupling and method for forming a hermetic seal between a component and a housing is provided in which a mechanical joint is formed between an exposed interior surface of the component and an exterior surface of a protrusion on the housing. The coefficients of thermal expansion of the connector and the housing are chosen such that the solder joint is in compression during cool down of the solder.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: May 31, 2005
    Assignee: Special Hermetic Products, Inc.
    Inventors: John A. Pollock, Anthony DeSantis
  • Publication number: 20050085102
    Abstract: A coupling and method for forming a hermetic seal between a component and a housing is provided in which a mechanical joint is formed between an exposed interior surface of the component and an exterior surface of a protrusion on the housing. The coefficients of thermal expansion of the connector and the housing are chosen such that the solder joint is in compression during cool down of the solder.
    Type: Application
    Filed: August 10, 2004
    Publication date: April 21, 2005
    Inventors: John Pollock, Anthony DeSantis
  • Publication number: 20050052758
    Abstract: A system and method of forming a hermetic seal between a lens or window and a lid, which minimizes bending moments, and therefore, bifringance on the window or lens is disclosed. This is accomplished by use of a transition member, specific geometries, and selection of the coefficient of thermal expansion of the materials to insure that the solder joint is in compression on cool down and solder strains are maintained within acceptable limits. The transition member may be soldered or welded to lid or integral through machining.
    Type: Application
    Filed: August 10, 2004
    Publication date: March 10, 2005
    Inventors: John Pollock, Anthony DeSantis
  • Patent number: 6821145
    Abstract: A hermetically sealed connector and method for providing the same is provided. Generally, the connector contains a header having a series of pins secured therein, wherein the header has an upper portion that extends in a direction perpendicular to a central axis of a pin within the series of pins. The header also has a lower lip portion that extends in a direction perpendicular to the upper lip portion. The connector also contains an outer body having a series of clearance layers therein that are defined by an inner wall of the outer body, wherein each clearance layer within the series of clearance layers has an associated diameter, and wherein the header is connected to a first portion of the inner wall via a solder joint that extends from the lower lip portion of the header to the first portion of the inner wall. The first portion of the inner wall also has at least two different diameters.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: November 23, 2004
    Assignee: Special Hermetic Products, Inc.
    Inventors: John A. Pollock, Anthony DeSantis
  • Patent number: 5811315
    Abstract: A method of forming and planarizing a deep isolation trench in a silicon-on-insulator (SOI) structure begins with a base semiconductor substrate, a buried insulator layer formed on the base semiconductor substrate, and an active silicon layer formed on the buried insulator layer. First, an ONO layer is formed on the active silicon layer. The ONO layer includes a layer of field oxide, a first layer of silicon nitride and a layer of deposited hardmask oxide. A trench having sidewalls that extend to the buried oxide layer is formed. A layer of trench lining oxide is then formed on the exposed sidewalls of the trench. Then, a second layer of silicon nitride is conformally formed on the substrate.
    Type: Grant
    Filed: March 13, 1997
    Date of Patent: September 22, 1998
    Assignee: National Semiconductor Corporation
    Inventors: Wipawan Yindeepol, Joel McGregor, Rashid Bashir, Kevin Brown, Joseph Anthony DeSantis