Abstract: A solution for managing a circuit design, which enables a cell to be incrementally placed in the circuit design based on a resulting wiring distance is provided. A cell to be placed in the circuit design is obtained along with a corresponding set of nets in the circuit design to which the cell is to be connected. A routing grid, which defines a plurality of tiles in the circuit design for consideration in placing the cell, can be generated based on the set of nets for the cell. A wire distance measure can be calculated for each of the tiles in the routing grid using the set of nets. The wire distance measure is then used to identify a target tile for placing the cell. The target tile can be used to find an exact and/or rough placement for the cell.

Abstract: A method and system of designing an electronic circuit includes dividing a chip area of a design into a plurality of bins, identifying a candidate bin in the plurality of bins, and performing an area reduction on the candidate bin.

Abstract: Computationally efficient methods and systems for optimizing an integrated circuit (IC) design by targeting only a limited subsection of buffer trees in the buffer system for optimization are provided. By making intelligent decisions about which buffer trees to optimize, greater gains in design efficiency (e.g., as measured by reduced delays and/or wire length) may be realized at greatly reduced computational times when compared to conventional techniques that attempt to optimize each buffer tree.

Abstract: A system and method are proposed for estimating interconnect delay in an Integrated Circuit (IC). A formula for effective capacitance is derived which considers the effect of slew as well as resistive shielding of capacitance, thus yielding more accurate delays for both the interconnects and the source driver (transistor gate). In the system and method, a resistor-capacitor (RC) tree model is used for iterative calculations of effective capacitance and slew for each RC tree node. The effective capacitance is determined for each node by proceeding outward from the source to the sinks, and the slew for each node is determined, using the effective capacitances just determined, by proceeding inward from the sinks to the source node. Once the source node slew determined at a previous iteration is within a specified threshold of the source node slew in the present iteration, the method stops and stores the present iteration values as the final estimates.