Abstract: An electronic system includes a multiple POL regulators that supply a regulated voltage to a component within the electronic system. A phase spreading scheme may be implemented so that the POL regulators operate under various phases to reduce voltage noise, high input capacitance, and high radiated emissions. One phase spreading scheme includes a single POL regulator controlling phase spreading so that the other POL regulators operate under different phases. Another phase spreading scheme includes an upstream POL regulator determining a phase offset that may be passed to a downstream POL regulator so that the downstream POL regulator may operate under a different phase relative to the upstream POL regulator.

Abstract: A system includes a first networking devices, a multiplexer, a second networking device, and a third networking device. The first networking device includes a pair of ports operational up to a first throughput. The multiplexer includes an input port connected to a port of the first networking device, and a pair of output ports. The second networking device includes an output port connected to a port of the first networking device and to an output port of the multiplexer, and operational up to a second throughput greater than the first throughput. The third networking device includes an output port connected to an output port of the multiplexer, and operational up to a third throughput no greater than the first throughput.

Abstract: An electronic system includes a multiple POL regulators that supply a regulated voltage to a component within the electronic system. A phase spreading scheme may be implemented so that the POL regulators operate under various phases to reduce voltage noise, high input capacitance, and high radiated emissions. One phase spreading scheme includes a single POL regulator controlling phase spreading so that the other POL regulators operate under different phases. Another phase spreading scheme includes an upstream POL regulator determining a phase offset that may be passed to a downstream POL regulator so that the downstream POL regulator may operate under a different phase relative to the upstream POL regulator.

Abstract: Ethernet physical sublayer (PHY) devices each provide PHY register data. One or more of the Ethernet PHY devices are connected to each of one or more management data input/output (MDIO)/management data clock (MDC) interfaces to which a number of MDIO/MDC controllers are connected. Each MDIO/MDC controller polls a corresponding MDIO/MDC interface to receive the PHY register data from the one or more Ethernet PHY devices connected thereto. The MDIO/MDC controllers store portions of the PHY register data received from the Ethernet PHY devices to a memory to which an interface is connected. A processor connected to the interface accesses the portions of the PHY register data stored to the memory. The processor can retrieve the portions of the PHY register data over the interface more quickly than the MDIO/MDC controllers can retrieve the PHY register data over the MDIO/MDC interfaces.

Abstract: An electronic system includes a multiple POL regulators that supply a regulated voltage to a component within the electronic system. A phase spreading scheme may be implemented so that the POL regulators operate under various phases to reduce voltage noise, high input capacitance, and high radiated emissions. One phase spreading scheme includes a single POL regulator controlling phase spreading so that the other POL regulators operate under different phases. Another phase spreading scheme includes an upstream POL regulator determining a phase offset that may be passed to a downstream POL regulator so that the downstream POL regulator may operate under a different phase relative to the upstream POL regulator.

Abstract: A breakout cable includes a data-lane module comprising a plurality of data lanes configured to send and receive a plurality of data signals, a plurality of breakout modules, and a plurality cables. Each breakout module is associated with a data lane and each cable interfaces with the data-lane module and a corresponding data lane to send and receive the plurality of signals between the data-lane module and a corresponding breakout module at a nominal 25 Gbps or a nominal 100 Gbps. In various embodiments, the data-lane module connects to a host and each of the plurality of modules connects to one or more system(s) to enable host-to-system(s) communications and system(s)-to-host communications at a nominal 100 Gbps or a nominal 400 Gbps.

Abstract: A cable assembly can include a single C form-factor pluggable (CFP) connector adhering to a CFP multi-source agreement (MSA), and providing a maximum bandwidth of between 100 and 120 gigabits-per-second (Gbps) over ten-to-twelve lanes. The cable assembly can include, for instance, one, two, or three quad small form-factor pluggable (QSFP/QSFP+) connectors adhering to a QSFP/QSFP+ MSA, and each providing a maximum bandwidth of forty Gbps over four lanes. The cable assembly can include one or more cables equal in number to the QSFP/QSFP+ connectors and each connecting the single CFP connector to the one of the QSFP/QSFP+ connectors. The four lanes over which each QSFP/QSFP+ connector provides the maximum bandwidth of forty Gbps corresponds to a different four of the ten-to-twelve lanes over which the single CFP connector provides the maximum bandwidth of between 100 and 120 Gbps.

Abstract: Ethernet physical sublayer (PHY) devices each provide PHY register data. One or more of the Ethernet PHY devices are connected to each of one or more management data input/output (MDIO)/management data clock (MDC) interfaces to which a number of MDIO/MDC controllers are connected. Each MDIO/MDC controller polls a corresponding MDIO/MDC interface to receive the PHY register data from the one or more Ethernet PHY devices connected thereto. The MDIO/MDC controllers store portions of the PHY register data received from the Ethernet PHY devices to a memory to which an interface is connected. A processor connected to the interface accesses the portions of the PHY register data stored to the memory. The processor can retrieve the portions of the PHY register data over the interface more quickly than the MDIO/MDC controllers can retrieve the PHY register data over the MDIO/MDC interfaces.

Abstract: An apparatus for enclosing an electronic component to a base comprising, an enclosure attached to a base and surrounding an electronic component. The enclosure divided into a first portion and a second portion along a first plane substantially parallel to the base. The second portion of the enclosure is attached to the base. The first portion of the enclosure is attached to the second portion of the enclosure. The enclosure including one or more extruding elements on an exterior surface of the enclosure. The one or more extruding elements on the exterior surface of the enclosure increases an exterior surface area of the enclosure facilitating dissipation of heat from the electronic component.

Abstract: A system to recover a multimaster serial single-ended bus and a faulted connected device includes a director device connected to the faulted connected device via the multimaster serial single-ended bus. The director device includes a central processing unit, a field programmable gate array, and a management module in communication with the faulted connected device, the management module configured to recover the faulted connected device and the multimaster serial single-ended bus. The management module may transmit a clock pulse to the faulted connected device if the faulted connected device is holding a data line (SDA) low, transmit a stop command to the faulted connected device if the faulted connected device is holding SDA low and/or read and compare a register value in the faulted device against an expected value to determine if the faulted device and the multimaster serial single-ended bus have been recovered.

Abstract: A breakout cable includes a data-lane module comprising a plurality of data lanes configured to send and receive a plurality of data signals, a plurality of breakout modules, and a plurality cables. Each breakout module is associated with a data lane and each cable interfaces with the data-lane module and a corresponding data lane to send and receive the plurality of signals between the data-lane module and a corresponding breakout module at a nominal 25 Gbps or a nominal 100 Gbps. In various embodiments, the data-lane module connects to a host and each of the plurality of modules connects to one or more system(s) to enable host-to-system(s) communications and system(s)-to-host communications at a nominal 100 Gbps or a nominal 400 Gbps.

Abstract: A system includes a first networking devices, a multiplexer, a second networking device, and a third networking device. The first networking device includes a pair of ports operational up to a first throughput. The multiplexer includes an input port connected to a port of the first networking device, and a pair of output ports. The second networking device includes an output port connected to a port of the first networking device and to an output port of the multiplexer, and operational up to a second throughput greater than the first throughput. The third networking device includes an output port connected to an output port of the multiplexer, and operational up to a third throughput no greater than the first throughput.

Abstract: Ethernet physical sublayer (PHY) devices each provide PHY register data. One or more of the Ethernet PHY devices are connected to each of one or more management data input/output (MDIO)/management data clock (MDC) interfaces to which a number of MDIO/MDC controllers are connected. Each MDIO/MDC controller polls a corresponding MDIO/MDC interface to receive the PHY register data from the one or more Ethernet PHY devices connected thereto. The MDIO/MDC controllers store portions of the PHY register data received from the Ethernet PHY devices to a memory to which an interface is connected. A processor connected to the interface accesses the portions of the PHY register data stored to the memory. The processor can retrieve the portions of the PHY register data over the interface more quickly than the MDIO/MDC controllers can retrieve the PHY register data over the MDIO/MDC interfaces.

Abstract: An electronic system includes a multiple POL regulators that supply a regulated voltage to a component within the electronic system. A phase spreading scheme may be implemented so that the POL regulators operate under various phases to reduce voltage noise, high input capacitance, and high radiated emissions. One phase spreading scheme includes a single POL regulator controlling phase spreading so that the other POL regulators operate under different phases. Another phase spreading scheme includes an upstream POL regulator determining a phase offset that may be passed to a downstream POL regulator so that the downstream POL regulator may operate under a different phase relative to the upstream POL regulator.

Abstract: A cable assembly can include a single C form-factor pluggable (CFP) connector adhering to a CFP multi-source agreement (MSA), and providing a maximum bandwidth of between 100 and 120 gigabits-per-second (Gbps) over ten-to-twelve lanes. The cable assembly can include, for instance, one, two, or three quad small form-factor pluggable (QSFP/QSFP+) connectors adhering to a QSFP/QSFP+ MSA, and each providing a maximum bandwidth of forty Gbps over four lanes. The cable assembly can include one or more cables equal in number to the QSFP/QSFP+ connectors and each connecting the single CFP connector to the one of the QSFP/QSFP+ connectors. The four lanes over which each QSFP/QSFP+ connector provides the maximum bandwidth of forty Gbps corresponds to a different four of the ten-to-twelve lanes over which the single CFP connector provides the maximum bandwidth of between 100 and 120 Gbps.

Abstract: A pair of ports of a first networking device operate up to a first throughput. An input port of a multiplexer connects to one of these ports, and the multiplexer also has a pair of output ports. An output port of another, second network device connects to one of the first networking device's and also to one of the multiplexer's output ports. These ports operate up to a second, greater throughput. An output port of yet another, third network device also connects to one of the multiplexer's output ports, and operates up to a third throughput no greater than the first throughput.

Abstract: A cable assembly can include a single C form-factor pluggable (CFP) connector adhering to a CFP multi-source agreement (MSA), and providing a maximum bandwidth of between 100 and 120 gigabits-per-second (Gbps) over ten-to-twelve lanes. The cable assembly can include, for instance, one, two, or three quad small form-factor pluggable (QSFP/QSFP+) connectors adhering to a QSFP/QSFP+ MSA, and each providing a maximum bandwidth of forty Gbps over four lanes. The cable assembly can include one or more cables equal in number to the QSFP/QSFP+ connectors and each connecting the single CFP connector to the one of the QSFP/QSFP+ connectors. The four lanes over which each QSFP/QSFP+ connector provides the maximum bandwidth of forty Gbps corresponds to a different four of the ten-to-twelve lanes over which the single CFP connector provides the maximum bandwidth of between 100 and 120 Gbps.

Abstract: A system to recover a multimaster serial single-ended bus and a faulted connected device includes a director device connected to the faulted connected device via the multimaster serial single-ended bus. The director device includes a central processing unit, a field programmable gate array, and a management module in communication with the faulted connected device, the management module configured to recover the faulted connected device and the multimaster serial single-ended bus. The management module may transmit a clock pulse to the faulted connected device if the faulted connected device is holding a data line (SDA) low, transmit a stop command to the faulted connected device if the faulted connected device is holding SDA low and/or read and compare a register value in the faulted device against an expected value to determine if the faulted device and the multimaster serial single-ended bus have been recovered.

Abstract: A printed circuit board (PCB) stackup includes conductive layers and insulating layers interleaved among the conductive layers. The conductive layers include one or more power layers, one or more ground layers, one or more high-frequency layers, and one or more low-frequency layers. One or more first signals having one or more first frequencies greater than a first threshold are communicated over the high-frequency layers. One or more second signals having one or more second frequencies less than a second threshold are communicated over the low-frequency layers. Each second frequency is less than each first frequency. The insulating layers include one or more core layers and one or more prepreg layers arranged in alternating fashion. Each insulating layer adjacent to any high-frequency layer has a first material type. Each insulating layer not adjacent to any high-frequency layer has a second material type different than the first material type.

Abstract: An apparatus for enclosing an electronic component to a base comprising, an enclosure attached to a base and surrounding an electronic component. The enclosure divided into a first portion and a second portion along a first plane substantially parallel to the base. The second portion of the enclosure is attached to the base. The first portion of the enclosure is attached to the second portion of the enclosure. The enclosure including one or more extruding elements on an exterior surface of the enclosure. The one or more extruding elements on the exterior surface of the enclosure increases an exterior surface area of the enclosure facilitating dissipation of heat from the electronic component.