Patents by Inventor Anthony E. Ciesla

Anthony E. Ciesla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fractional-N spread spectrum state machine
    Patent number: 9244484
    Abstract: Embodiments of the present invention may be realized in a fractional-N spread spectrum clock (SSC) generator utilizing an SSC state machine generating a single clock gating signal to drive a fractional-N phase locked loop (PLL) frequency multiplier to generate an SSC output clock. The SSC generator leverages upon the development of the digital PLL to implement the SSC generator within the final core PLL. The SSC generator only requires a relatively low base frequency reference clock and digital programming including an SSC rate and a modulation definition signal to produce the fractional-N spread spectrum output clock. The SSC generator results in cost savings through a high frequency SSC output clock generator that utilizes a relatively slow reference clock without the need for multiple high frequency clocks or multiple feedback clocks to drive the PLL.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: January 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Anthony E. Ciesla, Paul D. Muench
  • FRACTIONAL-N SPREAD SPECTRUM STATE MACHINE
    Publication number: 20150160687
    Abstract: Embodiments of the present invention may be realized in a fractional-N spread spectrum clock (SSC) generator utilizing an SSC state machine generating a single clock gating signal to drive a fractional-N phase locked loop (PLL) frequency multiplier to generate an SSC output clock. The SSC generator leverages upon the development of the digital PLL to implement the SSC generator within the final core PLL. The SSC generator only requires a relatively low base frequency reference clock and digital programming including an SSC rate and a modulation definition signal to produce the fractional-N spread spectrum output clock. The SSC generator results in cost savings through a high frequency SSC output clock generator that utilizes a relatively slow reference clock without the need for multiple high frequency clocks or multiple feedback clocks to drive the PLL.
    Type: Application
    Filed: December 11, 2013
    Publication date: June 11, 2015
    Applicant: International Business Machines Corporation
    Inventors: Anthony E. Ciesla, Paul D. Muench