Abstract: A disk drive is disclosed comprising a disk comprising a plurality of servo tracks defined by servo sectors, a head actuated over the disk, and control circuitry comprising a read channel. A plurality of data tracks are defined relative to the servo tracks, wherein each data track comprises a plurality of segments. The read channel is configured into a read mode in order to first read a first segment of a first data track. During the first read, a quality metric is generated at periodic points along the first segment. After the first read, the read channel is configured into a non-read mode for a predetermined interval. After the predetermined interval, the read channel is configured into the read mode in order to second read the first segment of the first data track and generate the quality metric at the periodic points along the first segment.

Abstract: A data flow control and bridging architecture that enhances the performance of removable data storage systems. In one implementation, the present invention provides a bypass bus implementation where the data transfer phase associated with select commands occurs directly between the host computing system and the target removable data storage unit. In one implementation, the present invention further provides a data flow and bridging architecture that emulates a removable media interface, such as the ATAPI interface, to the host computing system, and translates these commands for a target removable storage unit that implements a fixed media interface, such as the ATA interface. In yet another implementation, the present invention provides a data flow and bridging architecture that supports the serial ATA interface.

Abstract: A data flow control and bridging architecture that enhances the performance of removable data storage systems. In one implementation, the present invention provides a bypass bus implementation where the data transfer phase associated with select commands occurs directly between the host computing system and the target removable data storage unit. In one implementation, the present invention further provides a data flow and bridging architecture that emulates a removable media interface, such as the ATAPI interface, to the host computing system, and translates these commands for a target removable storage unit that implements a fixed media interface, such as the ATA interface. In yet another implementation, the present invention provides a data flow and bridging architecture that supports the serial ATA interface.

Abstract: A data flow control and bridging architecture that enhances the performance of removable data storage systems. In one implementation, the present invention provides a bypass bus implementation where the data transfer phase associated with select commands occurs directly between the host computing system and the target removable data storage unit. In one implementation, the present invention further provides a data flow and bridging architecture that emulates a removable media interface, such as the ATAPI interface, to the host computing system, and translates these commands for a target removable storage unit that implements a fixed media interface, such as the ATA interface. In yet another implementation, the present invention provides a data flow and bridging architecture that supports the serial ATA interface.

Abstract: A data flow control and bridging architecture that enhances the performance of removable data storage systems. In one implementation, the present invention provides a bypass bus implementation where the data transfer phase associated with select commands occurs directly between the host computing system and the target removable data storage unit. In one implementation, the present invention further provides a data flow and bridging architecture that emulates a removable media interface, such as the ATAPI interface, to the host computing system, and translates these commands for a target removable storage unit that implements a fixed media interface, such as the ATA interface. In yet another implementation, the present invention provides a data flow and bridging architecture that supports the serial ATA interface.

Abstract: A data flow control and bridging architecture that enhances the performance of removable data storage systems. In one implementation, the present invention provides a bypass bus implementation where the data transfer phase associated with select commands occurs directly between the host computing system and the target removable data storage unit. In one implementation, the present invention further provides a data flow and bridging architecture that emulates a removable media interface, such as the ATAPI interface, to the host computing system, and translates these commands for a target removable storage unit that implements a fixed media interface, such as the ATA interface. In yet another implementation, the present invention provides a data flow and bridging architecture that supports the serial ATA interface.

Abstract: The present invention, in particular embodiments, is directed to methods, apparatuses and systems directed to the authentication of cartridge-based storage media. In a particular embodiment, the present invention provides authentication passwords that are stored on authorized cartridge-based hard disc drives. The authentication password, in one embodiment, is a hash of an interleaved combination of a cartridge-based hard disc drive's serial number and model number strings. Upon insertion of a locked cartridge-based hard disc drive into a carrier, carrier logic obtains the serial number and model number strings of the hard disc drive and generates a password additionally using a base string. The carrier logic then attempts to unlock/authenticate the cartridge-based hard disc drive with the newly-generated password. Authentication occurs with an authorized cartridge as the password contained in the associated hard disc drive will match the password sent by the carrier logic.

Abstract: A data flow control and bridging architecture that enhances the performance of removable data storage systems. In one implementation, the present invention provides a bypass bus implementation where the data transfer phase associated with select commands occurs directly between the host computing system and the target removable data storage unit. In one implementation, the present invention further provides a data flow and bridging architecture that emulates a removable media interface, such as the ATAPI interface, to the host computing system, and translates these commands for a target removable storage unit that implements a fixed media interface, such as the ATA interface. In yet another implementation, the present invention provides a data flow and bridging architecture that supports the serial ATA interface.

Abstract: A data flow control and bridging architecture that enhances the performance of removable data storage systems. In one implementation, the present invention provides a bypass bus implementation where the data transfer phase associated with select commands occurs directly between the host computing system and the target removable data storage unit. In one implementation, the present invention further provides a data flow and bridging architecture that emulates a removable media interface, such as the ATAPI interface, to the host computing system, and translates these commands for a target removable storage unit that implements a fixed media interface, such as the ATA interface. In yet another implementation, the present invention provides a data flow and bridging architecture that supports the serial ATA interface.

Abstract: A data flow control and bridging architecture that enhances the performance of removable data storage systems. In one implementation, the present invention provides a bypass bus implementation where the data transfer phase associated with select commands occurs directly between the host computing system and the target removable data storage unit. In one implementation, the present invention further provides a data flow and bridging architecture that emulates a removable media interface, such as the ATAPI interface, to the host computing system, and translates these commands for a target removable storage unit that implements a fixed media interface, such as the ATA interface. In yet another implementation, the present invention provides a data flow and bridging architecture that supports the serial ATA interface.

Abstract: A data flow control and bridging architecture that enhances the performance of removable data storage systems. In one implementation, the present invention provides a bypass bus implementation where the data transfer phase associated with select commands occurs directly between the host computing system and the target removable data storage unit. In one implementation, the present invention further provides a data flow and bridging architecture that emulates a removable media interface, such as the ATAPI interface, to the host computing system, and translates these commands for a target removable storage unit that implements a fixed media interface, such as the ATA interface. In yet another implementation, the present invention provides a data flow and bridging architecture that supports the serial ATA interface.

Abstract: An external storage device includes a power management system. The power management system comprises an energy storage circuit which stores energy from a power source and provides additional power to the external storage device. The external storage device further comprises a microcontroller which determines whether the combined power from the power source and the energy storage circuit is sufficient for the external storage device to perform a particular command received from a host computer. If the power from the power source and the energy storage circuit is insufficient, the microcontroller causes the external storage device to either suspend the command until sufficient energy is stored on the energy storage circuit to execute the command or execute the command at a rate slower than a normal rate.

Abstract: A high speed, integrated circuit microprocessor includes a microinstruction sequencer for sequentially generating a plurality of N control words per period, each control word having a plurality of M bits. The microsequencer includes a storage register in the integrated circuit, having a plurality of M times N storage locations, for storing a microinstruction containing the N control words. The microsequencer also includes an N bit shift register in the integrated circuit, having N sequential outputs and a clock input with a cycle time equal to 1/N of the period, for propagating a binary bit therethrough to sequentially provide an enabling bit to each of the respective N outputs thereof. A plurality of M logic stages is also included in the integrated circuit, each stage including a plurality of two-input N AND gates. An i.sup.th one of these N AND gates in each stage has a first input connected to an i.sup.