Abstract: A three-dimensional coil inductor is disclosed. The inductor includes a substrate; a set of lower electrically conductive traces positioned on the substrate; a core placed over the lower traces; a set of side electrically conductive traces laid on the core and the lower traces; and a set of upper electrically conductive traces attached to the side traces so as to form the inductor. Fabrication of the inductor includes the steps of forming a set of lower traces on a substrate; positioning a core over the lower traces; forming a set of side traces on the core; connecting the side traces to the lower traces; forming a set of upper traces on the core; and connecting the upper traces to the side traces so as to form a coil structure.

Abstract: A process which vastly improves the 3-D patterning capability of laser pantography (computer controlled laser direct-write patterning). The process uses commercially available electrodeposited photoresist (EDPR) to pattern 3-D surfaces. The EDPR covers the surface of a metal layer conformally, coating the vertical as well as horizontal surfaces. A laser pantograph then patterns the EDPR, which is subsequently developed in a standard, commercially available developer, leaving patterned trench areas in the EDPR. The metal layer thereunder is now exposed in the trench areas and masked in others, and thereafter can be etched to form the desired pattern (subtractive process), or can be plated with metal (additive process), followed by a resist stripping, and removal of the remaining field metal (additive process). This improved laser pantograph process is simpler, faster, move manufacturable, and requires no micro-machining.

Abstract: A process for fabricating a nanofilament field emission device. The process enables the formation of high aspect ratio, electroplated nanofilament structure devices for field emission displays wherein a via is formed in a dielectric layer and is self-aligned to a via in the gate metal structure on top of the dielectric layer. The desired diameter of the via in the dielectric layer is on the order of 50-200 nm, with an aspect ratio of 5-10. In one embodiment, after forming the via in the dielectric layer, the gate metal is passivated, after which a plating enhancement layer is deposited in the bottom of the via, where necessary. The nanofilament is then electroplated in the via, followed by removal of the gate passification layer, etch back of the dielectric, and sharpening of the nanofilament. A hard mask layer may be deposited on top of the gate metal and removed following electroplating of the nanofilament.

Abstract: An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus.

Abstract: A method for sharpening field emitter tips by electroetching/polishing. In gated field emitters, it is very important to initiate electron emission at the lowest possible voltage and thus the composition of the emitter and the gate, as well as the emitter-gate structure, are important factors. This method of sharpening the emitter tips uses the grid as a counter electrode in electroetching of the emitters, which can produce extremely sharp emitter tips as well as remove asperities and other imperfections in the emitters, each in relation to the specific grid hole in which it resides. This has the effect of making emission more uniform among the emitters as well as lowering the turn-on voltage.

Abstract: Electrochemical formation of field emitters, particularly useful in the fabrication of flat panel displays. The fabrication involves field emitting points in a gated field emitter structure. Metal field emitters are formed by electroplating and the shape of the formed emitter is controlled by the potential imposed on the gate as well as on a separate counter electrode. This allows sharp emitters to be formed in a more inexpensive and manufacturable process than vacuum deposition processes used at present. The fabrication process involves etching of the gate metal and the dielectric layer down to the resistor layer, and then electroplating the etched area and forming an electroplated emitter point in the etched area.

Abstract: Spacers for applications such as field emission flat panel displays and vacuum microelectronics, and which involves the application of aerogel/xerogel technology to the formation of the spacer. In a preferred approach the method uses a mold and mold release agent wherein the gel precursor is a liquid which can be applied to the mold filling holes which expose the substrate (either the baseplate or the faceplate). A release agent is applied to the mold prior to precursor application to ease removal of the mold after formation of the dielectric spacer. The shrinkage of the gel during solvent extraction also improves mold removal. The final spacer material is a good dielectric, such as silica, secured to the substrate.

Abstract: A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets.For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.

Abstract: In a process for fabricating planarized thin film metal interconnects for integrated circuit structures, a planarized metal layer is etched back to the underlying dielectric layer by electropolishing, ion milling or other procedure. Electropolishing reduces processing time from hours to minutes and allows batch processing of multiple wafers. The etched back planarized thin film interconnect is flush with the dielectric layer.

Abstract: A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow "dummy chips" are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned o the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.

Abstract: Microchannel cooling is applied to flip-chip bonded integrated circuits, in a manner which maintains the advantages of flip-chip bonds, while overcoming the difficulties encountered in cooling the chips. The technique is suited to either multichip integrated circuit boards in a plane, or to stacks of circuit boards in a three dimensional interconnect structure. Integrated circuit chips are mounted on a circuit board using flip-chip or control collapse bonds. A microchannel structure is essentially permanently coupled with the back of the chip. A coolant delivery manifold delivers coolant to the microchannel structure, and a seal consisting of a compressible elastomer is provided between the coolant delivery manifold and the microchannel structure. The integrated circuit chip and microchannel structure are connected together to form a replaceable integrated circuit module which can be easily decoupled from the coolant delivery manifold and the circuit board.

Abstract: Disclosed is a process for selective metal deposition comprising of the steps of:a. formation of an initial surface on a substrate, said initial surface being comprised of at least two layers of which the uppermost is inert,b. exposing the surface to a source of heat in pre-determined places wherein surface activation is desired, andc. deposition of metal on activated portions of said surface.

Abstract: In an electropolishing or electrolytic etching apparatus the anode is separated from the cathode to prevent bubble transport to the anode and to produce a uniform current distribution at the anode by means of a solid nonconducting anode-cathode barrier. The anode extends into the top of the barrier and the cathode is outside the barrier. A virtual cathode hole formed in the bottom of the barrier below the level of the cathode permits current flow while preventing bubble transport. The anode is rotatable and oriented horizontally facing down. An extended anode is formed by mounting the workpiece in a holder which extends the electropolishing or etching area beyond the edge of the workpiece to reduce edge effects at the workpiece. A reference electrode controls cell voltage. Endpoint detection and current shut-off stop polishing. Spatially uniform polishing or etching can be rapidly performed.

Abstract: Amplified spontaneous emission is substantially reduced in a novel optical amplifier wherein the gain medium is disposed within a converging region of the coherent signal, which converging region terminates in a waist at or near a limiting stop or saturable absorber. In contrast to the converging coherent signal flux, the amplified spontaneous emission flux is nonconverging and therefore most of the latter is removed by a spatial filter or saturable absorber.

Abstract: In the method of separating isotopes wherein a desired isotope species is selectively deflected out of a beam of mixed isotopes by irradiating the beam with a directed beam of light of narrowly defined frequency which is selectively absorbed by the desired species, the improvement comprising irradiating the deflected beam with light from other light sources whose frequencies are selected to cause the depopulation of any metastable excited states.