Abstract: The out-of-lock condition of a digital phase locked loop is detected during a plurality of states such that single bit discrepancies, such as a noise pulse, are ignored, and thus the tolerable range of phase detection error is broadened. The present invention is adaptable for use with typical applications of digital phase locked loops, and can be used to control the phase detector of the digital phase locked loop such that error voltages will be introduced into the loop only during selected states.

Abstract: A programmable logic controller includes a read/write memory for storing multi bit instructions which direct computations in the controller in response to a programming keyboard module connected to the controller for encoding instructions to be stored in controller memory. Keyboard commands transfer instructions from the module to said memory in an ordered array. Instructions are read from memory serially, cyclically and non destructively for operation of the controller. A keyboard insert command inserts a new instruction at a designated address in memory and sequentially shifts each serially accessed instruction in memory stored at an address beyond the designated address to a memory address once removed.