Patents by Inventor Anthony Fryars

Anthony Fryars has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080235545
    Abstract: Mission circuitry provided to implement desired data processing operations in an integrated circuit apparatus is tested by using a plurality of scan paths to subject the mission circuitry to production testing before the integrated circuit apparatus is deployed in a mission environment. The plurality of scan paths are re-used to subject the mission circuitry to further testing while the integrated circuit apparatus is deployed in a mission environment.
    Type: Application
    Filed: March 5, 2008
    Publication date: September 25, 2008
    Inventors: Vinay Burjinroppa Jayaram, Anthony Fryars
  • Publication number: 20060107144
    Abstract: A circuit and method for reducing the power consumed by module-based scan testing. In one embodiment constant data is provided to inputs, such as 33, of scan chains not used in testing, such as 32. Another embodiment is a method whereby transitions in a subset of scan chains, such as 32, are minimized through the use of constant input data.
    Type: Application
    Filed: December 16, 2005
    Publication date: May 18, 2006
    Inventors: Jayashree Saxena, Kenneth Butler, Atul Jain, Anthony Fryars, Graham Hetherington
  • Patent number: 6654920
    Abstract: An integrated circuit (10) comprising combinational circuitry (13). The integrated circuit further comprises a plurality of scan channels (SC1 through SC4). Each of the plurality of scan channels comprises a number of scan elements (EC11 through EC45). For any of the plurality of scan channels having a number of scan elements greater than one element, the scan channel comprises a first element in the scan channel and a last element in the scan channel. For any of the plurality of scan channels having a number of scan elements equal to one element, the one element is both a first element and a last element in the scan channel. Further, selected ones of the scan elements are coupled to affect operation of the combinational circuitry. The integrated circuit further comprises circuitry (24) for coupling a predetermined pattern into the first element of each of the plurality of scan channels and circuitry (26) for detecting the predetermined pattern in the last element of each of the plurality scan channels.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: November 25, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Graham G. Hetherington, Anthony Fryars
  • Publication number: 20020170010
    Abstract: A circuit and method for reducing the power consumed by module-based scan testing. In one embodiment constant data is provided to inputs, such as 33, of scan chains not used in testing, such as 32. Another embodiment is a method whereby transitions in a subset of scan chains, such as 32, are minimized through the use of constant input data.
    Type: Application
    Filed: April 24, 2002
    Publication date: November 14, 2002
    Inventors: Jayashree Saxena, Kenneth M. Butler, Atul K. Jain, Anthony Fryars, Graham G. Hetherington