Abstract: A method and apparatus of a device that manages a thermal profile of a device by selectively throttling graphics processing unit operations of the device is described. In an exemplary embodiment, the device monitors the thermal profile of the device, where the device executes a plurality of processes that utilizes a graphics processing unit of the device. In addition, the plurality of processes include a high priority process and a low priority process. If the thermal profile of the device exceeds a thermal threshold, the device decreases a first GPU utilization for the low priority process and maintains a second GPU utilization for the high priority process. The device further executes the low priority process using the first GPU utilization with the GPU and executes the high priority process using the second GPU utilization with the GPU.

Abstract: A method and apparatus of a device that manages a thermal profile of a device by selectively throttling graphics processing unit operations of the device is described. In an exemplary embodiment, the device monitors the thermal profile of the device, where the device executes a plurality of processes that utilizes a graphics processing unit of the device. In addition, the plurality of processes include a high priority process and a low priority process. If the thermal profile of the device exceeds a thermal threshold, the device decreases a first GPU utilization for the low priority process and maintains a second GPU utilization for the high priority process. The device further executes the low priority process using the first GPU utilization with the GPU and executes the high priority process using the second GPU utilization with the GPU.

Abstract: Methods and apparatuses are disclosed that may provide graphics controllers with increased thermal granularity. The graphics controller may comprise a display memory, at least one display engine coupled to the display memory, and at least one execution unit coupled to the display memory, where the at least one execution unit may begin an idle period that varies based upon a thermal event.

Abstract: Some embodiments include a graphics processing with thermal management capabilities. The graphics processing unit may include a display controller, a microprocessing engine coupled to the display controller, and a clock circuit coupled to the display controller and the microprocessing engine. The clock circuit may further include a raw clock signal coupled to the display controller, a divider coupled to the raw clock signal, and a multiplexer coupled to the divider. The divider may generate a divided version of the raw clock signal, which may be coupled to the multiplexer along with the raw clock signal. The multiplexer may selectively provide the raw clock signal and/or the divided version of the clock signal to the microprocessing engine such that the microprocessing engine may receive a timing signal that is independent of operations of the graphics processing unit and result in fewer glitches.

Abstract: Methods and apparatuses are disclosed that may provide graphics controllers with increased thermal granularity. The graphics controller may comprise a display memory, at least one display engine coupled to the display memory, and at least one execution unit coupled to the display memory, where the at least one execution unit may begin an idle period that varies based upon a thermal event.

Abstract: Some embodiments include a graphics processing with thermal management capabilities. The graphics processing unit may include a display controller, a microprocessing engine coupled to the display controller, and a clock circuit coupled to the display controller and the microprocessing engine. The clock circuit may further include a raw clock signal coupled to the display controller, a divider coupled to the raw clock signal, and a multiplexer coupled to the divider. The divider may generate a divided version of the raw clock signal, which may be coupled to the multiplexer along with the raw clock signal. The multiplexer may selectively provide the raw clock signal and/or the divided version of the clock signal to the microprocessing engine such that the microprocessing engine may receive a timing signal that is independent of operations of the graphics processing unit and result in fewer glitches.