Abstract: A method for reducing overhead on a loop of a plurality of instructions is disclosed. The method includes providing a carry mask, the carry mask having a first value for the loop being performed at least the particular number of times minus one and a second value for at least a last instruction of the loop being performed a last time, providing addition logic, wherein the carry mask and a current instruction address of the plurality of instructions correspond to inputs of the addition logic and determining which of the plurality of instructions is to be executed using the carry mask to provide a resultant of the addition logic based on the carry mask and the current instruction address of the plurality of instructions.

Abstract: A design structure embodied in a machine readable storage medium designing, manufacturing, and/or testing a design that includes a multi-threaded processor that executes an instruction of a process of an executing program is provided. The multi-threaded processor includes at least a first and a second thread. First and second sets of source registers are respectively allocated to the first and second threads, and first and second sets of destination registers are respectively allocated to the first and second threads. A resource prefix configuration register includes mappings between each of the source and destination registers and the threads. The multi-threaded processor, during execution of the instruction by one of the first or the second threads of execution, accesses the source and destination registers based on the mapping, wherein at least one of the accessed registers is allocated to the other of the first or the second thread of execution.

Abstract: A system includes a multi-threaded processor that executes an instruction of a process of an executing program. The multi-threaded processor includes at least a first and a second thread. First and second sets of source registers are respectively allocated to the first and second threads, and first and second sets of destination registers are respectively allocated to the first and second threads. A resource prefix configuration register includes mappings between each of the source and destination registers and the threads. The multi-threaded processor, during execution of the instruction by one of the first or the second threads of execution, accesses the source and destination registers based on the mapping, wherein at least one of the accessed registers is allocated to the other of the first or the second thread of execution.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a system that includes a cache that stores information in a cache line for processing, wherein the cache line includes at least a first field configured to store an instruction or data and at least a second field configured to store parity information, a parity register that include a parameter indicative a whether parity generation and checking is disabled for the information in the cache line, and a processor that sets the second field in the cache line to include a value, which indicates a corresponding action to be performed, when the parameter in the parity register indicates that parity generation and checking is disabled for the cache line.

Abstract: A method includes checking a first parameter that indicates whether parity generation and checking for a at least a sub-portion of a cache line is disabled, setting at least one parity bit, corresponding to the sub-portion, in the cache line with a second parameter that indicates an action to perform when the first parameter indicates that parity generation and checking is disabled, passing the at least one set parity bit with the sub-portion to a processor for processing, and performing the action when the sub-portion is processed by the processor, wherein the processor performs the action.

Abstract: Management of hierarchical identifiers in simulation models and netlists is accomplished using a prefix compressor algorithm running on a general purpose computer processor. Full name compression is accomplished when hierarchy data and remainder data are split off and prefix compressed. Compressing prefixes of names in the hierarchy list is performed by comparing a previous entry to a current entry. Compressing prefixes of names in the name list is performed by running an output of compressing of prefixes of names in the hierarchy list and running an output of the compressing of prefixes of names in the name list through a standard compressor software application package. Decompressing of names uses sub operations inverse to the prefix compressor algorithm. The decompressing sub operations create a string pointed to by the prefix pointer and concatenated onto the string pointed to by the name pointer; and thus a full name is created.

Abstract: A method and system for testing a plurality of cores in an integrated circuit is disclosed. The method and system include providing a plurality of slave controllers a master controller. Each of the plurality of slave controllers is for testing at least one of the plurality of cores. The master controller is coupled with the plurality of slave controllers in a star configuration. The master controller is configured to allow test data to be input directly to a portion of the plurality of slave controllers in parallel. The portion of the plurality of slave controllers can include more than one slave controller.

Abstract: Dynamic routing of data to multiple processor complexes. PCI address space is subdivided among a plurality of processor complexes. Translation table entries at each processor complex determine which processor complex is to receive a DMA transfer, thereby enabling routing of DMA data to one I/O hub node while accessing translation table entries at another I/O hub node. Further, interrupt requests may be dynamically routed to multiple processor complexes.