Abstract: A process for placing non-continuous Dual Electron Injection Structures (DEIS) between two layers of polysilicon used to form an array of poly devices on an integrated circuit substrate. Separate masks are used to define Poly 1 and Poly 2 devices, respectively. The DEIS structure is disposed above the poly 1 devices. A silicon nitride (Si.sub.3 N.sub.4) layer is used to mask the DEIS structure and prevents it from oxidizing during certain processing steps. A thin layer of poly x is placed between the DEIS structure and the Si.sub.3 N.sub.4. The poly x layer forms a buffer and protects the DEIS during an etching step which removes the Si.sub.3 N.sub.4 layer.

Abstract: A method for forming thin film interconnection patterns atop substrates, particularly semiconductor substrates. It features the use of the passivation layer itself, typically glass, as a stable masking material to etch the conductive lines. Conversely, the metal conductor is used as a stable mask in etching the glass to form via holes. The process provides a practical resist system which is compatible with reactive ion etching or other dry etching process.