Patents by Inventor Anthony J. Konecni
Anthony J. Konecni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6660650Abstract: An embodiment of the instant invention is a method of fabricating an electronic device over a semiconductor substrate having an interconnecting structure comprised of aluminum, the method comprising the steps of: forming a conductive structure (layers 120, 122 and 128 of FIGS. 1a-1d) comprised of a metal; forming a dielectric layer (layer 130 of FIGS. 1a-1d) over the conductive structure, the dielectric layer having an upper surface; forming an opening in the dielectric layer so as to expose a portion of the conductive structure, the opening having sidewalls; selectively depositing an aluminum-containing conductive material (material 136 and 137 of FIG. 1c) in the opening; and performing an etchback process so as to remove any of the aluminum-containing conductive material formed on the hardmask and so as to etchback any portion of the aluminum-containing conductor which is situated over the upper surface of the dielectric layer.Type: GrantFiled: December 17, 1999Date of Patent: December 9, 2003Assignee: Texas Instruments IncorporatedInventors: Anthony J. Konecni, Wei-yung Hsu, Qi-zhong Hong
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Publication number: 20030168736Abstract: A method for selectively coupling a conductive material (60) to a contact region (32) of a semiconductor device (8) includes bombarding residual material (40) coupled to the contact region (32) with inert ions (44) at a first position associated with an integrated cluster tool (90) to increase the reactive surface area of the residual material (40). Hydrogen ions (46) are introduced at the first position for reaction with the residual material (40) to remove the residual material (40) from the contact region (32). The semiconductor device (8) is transferred in situ from the first position to a second position associated with the integrated cluster tool (90). The conductive material (60) is selectively coupled to the contact region (32) at the second position using chemical vapor deposition.Type: ApplicationFiled: March 17, 2003Publication date: September 11, 2003Inventors: Anthony J. Konecni, Girish A. Dixit
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Patent number: 6455419Abstract: An electronic device is provided that compromises a dielectric layer (12) disposed outwardly from a substrate (10). The dielectric layer (12) has at least one contact opening (14) formed through the dielectric layer (12). The device has an adhesion layer (16) disposed outwardly from the exposed surfaces of the dielectric layer (12) and the substrate (10). A first barrier layer (18) is formed outwardly from the adhesion layer (16). A second barrier layer (20) is formed outwardly from the first barrier layer (18). A conductive plug (24) fills the contact opening (14) and is disposed outwardly from the second barrier layer (20).Type: GrantFiled: September 9, 1999Date of Patent: September 24, 2002Assignee: Texas Instruments IncorporatedInventors: Anthony J. Konecni, Srikanth Bolnedi
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Publication number: 20020048926Abstract: A copper interconnect having a self-aligned aluminum barrier (124). After the copper interconnect lines (118) are formed, an aluminum layer (124) is selectively deposited over the surface of the copper interconnect lines (118), but not over the IMD (108). The aluminum barrier (124) may be converted to aluminum-oxide or aluminum-nitride.Type: ApplicationFiled: September 6, 2001Publication date: April 25, 2002Inventor: Anthony J. Konecni
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Publication number: 20010049192Abstract: A method for selectively coupling a conductive material (60) to a contact region (32) of a semiconductor device (8) includes bombarding residual material (40) coupled to the contact region (32) with inert ions (44) at a first position associated with an integrated cluster tool (90) to increase the reactive surface area of the residual material (40). Hydrogen ions (46) are introduced at the first position for reaction with the residual material (40) to remove the residual material (40) from the contact region (32). The semiconductor device (8) is transferred in situ from the first position to a second position associated with the integrated cluster tool (90). The conductive material (60) is selectively coupled to the contact region (32) at the second position using chemical vapor deposition.Type: ApplicationFiled: June 4, 2001Publication date: December 6, 2001Inventors: Anthony J. Konecni, Girish A. Dixit
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Patent number: 6291347Abstract: A system for constructing semiconductor devices is disclosed. The system comprises a wafer (102) having semiconductor devices (104), a bevel (108), an edge (110), a frontside (111), and a backside (112). The system also has a chamber (107), and a heater (106) coupled to the interior of the chamber (107) and operable to hold and heat the wafer (102). A showerhead (114) is also coupled to the interior of the chamber (107) and is operable to introduce a precursor gas (116) containing copper over the wafer (102). A shield (118) is coupled to the interior of the chamber (107) and is operable to partially shield the bevel (108), the edge (110), and the backside (112) of the wafer (102) from the precursor gas (116). There is an opening (122) in the chamber (107) through which a reactive backside gas (124) may be introduced under the wafer (102). A method for constructing semiconductor devices is disclosed. Step one calls for placing a wafer (102) on a heater (106) in a chamber (107).Type: GrantFiled: September 26, 2000Date of Patent: September 18, 2001Assignee: Texas Instruments IncorporatedInventors: Noel M. Russell, Anthony J. Konecni
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Patent number: 6215186Abstract: An electronic device is provided that compromises a dielectric layer (12) disposed outwardly from a substrate (10). The dielectric layer (12) has at least one contact opening (14) formed through the dielectric layer (12). The device has an adhesion layer (16) disposed outwardly from the exposed surfaces of the dielectric layer (12) and the substrate (10). A first barrier layer (18) is formed outwardly from the adhesion layer (16). A second barrier layer (20) is formed outwardly from the first barrier layer (18). A conductive plug (24) fills the contact opening (14) and is disposed outwardly from the second barrier layer (20).Type: GrantFiled: January 5, 1999Date of Patent: April 10, 2001Assignee: Texas Instruments IncorporatedInventors: Anthony J. Konecni, Srikanth Bolnedi
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Patent number: 6069072Abstract: A structure and method incorporating a CVD TiN barrier layer 230 over the aluminum plug 220 in order to prevent the high plug resistance caused by the blanket metal film stack 240, 250, and 260 deposition process. Unlike physical vapor deposited (PVD) TiN, CVD TiN 230 does not react with the aluminum 220 during annealing. CVD TiN has also been shown to be a better diffusion barrier for aluminum than PVD TiN. In addition, CVD TiN will disrupt any unfavorable grain boundary propagation through the aluminum plug which may act as a source of electromigration failure. Therefore, the CVD TiN 230 can increase the electromigration resistance, without increasing the contact/via resistance.Type: GrantFiled: April 15, 1998Date of Patent: May 30, 2000Assignee: Texas Instruments IncorporatedInventors: Anthony J. Konecni, Girish Anant Dixit
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Patent number: 5981382Abstract: An embodiment of the instant invention is a method of fabricating a conductive structure for electrically connecting one portion of a semiconductor device to another portion of the device, the method comprising the steps of: providing a continuous liner layer (step 104) of the semiconductor substrate, the liner layer comprised of CVD Al; forming a first conductor (step 106) on the liner layer, the first conductor formed using a source whose output power is in the range of 1 to 5 kW; and forming a second conductor (step 108) on the first conductor, the second conductor formed using a source whose output power is in the range of 10 to 20 kW. Preferably, the conductive structure is selected from the group consisting of: contact, via, and trench. In an alternative embodiment, a nucleation layer is formed (step 104) beneath the continuous liner layer. The nucleation layer is, preferably, comprised of titanium or a Ti/TiN stack.Type: GrantFiled: March 13, 1998Date of Patent: November 9, 1999Assignee: Texas Instruments IncorporatedInventors: Anthony J. Konecni, Noel Russell
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Patent number: 5849367Abstract: An elemental titanium-free liner and cavity cleansing process is provided that allows for the elimination of conventional sputter etch and elemental titanium depositions. A low power plasma etch provides for pre-conditioning/cleansing of cavities such as contacts and vias. A refractory metal is provided as a cavity liner. Preferably, the liner is comprised of several discrete refractory metal liner layers, each having a thickness of about 25-100 .ANG., that can be applied by CVD and/or PVD. A low power plasma cleanse is preferably interposed between each liner layer deposition. A suitable metal plug can be deposited and directed into the cavity to complete cavity filling. Preferably, the metal plug is an elemental aluminum or aluminum alloy plug that is deposited by CVD and force-filled into the cavity to reduce the incidence of micro-voids within the cavity.Elimination of the conventional sputter etch and the high temperature processing (temp..gtoreq..sup..about. 400.degree. C.Type: GrantFiled: December 11, 1996Date of Patent: December 15, 1998Assignee: Texas Instruments IncorporatedInventors: Girish A. Dixit, Anthony J. Konecni