Abstract: According to an exemplary embodiment, a wafer level package includes a device wafer including at least one device wafer contact pad and a device, and where the at least one device wafer contact pad is electrically connected to the device. The wafer level package includes a first polymer layer situated over the device wafer. The wafer level package includes at least one passive component situated over the first polymer layer and having a first terminal and a second terminal. The first terminal of the at least one passive component is electrically connected to the at least one device wafer contact pad. The wafer level package includes a second polymer layer situated over the at least one passive component. The wafer level package includes at least one polymer layer contact pad situated over the second polymer layer and electrically connected to the second terminal of the at least one passive component.

Abstract: According to an exemplary embodiment, a wafer level package includes a device wafer including at least one device wafer contact pad and a device, and where the at least one device wafer contact pad is electrically connected to the device. The wafer level package includes a first polymer layer situated over the device wafer. The wafer level package includes at least one passive component situated over the first polymer layer and having a first terminal and a second terminal. The first terminal of the at least one passive component is electrically connected to the at least one device wafer contact pad. The wafer level package includes a second polymer layer situated over the at least one passive component. The wafer level package includes at least one polymer layer contact pad situated over the second polymer layer and electrically connected to the second terminal of the at least one passive component.

Abstract: A method for overmolding a ceramic substrate for a semiconductor chip or other electrical device, and a resulting package, are disclosed. In one embodiment, plural ceramic substrate panels having a matrix of semiconductor chips thereon are precisely located on and attached to a temporary support member using an alignment tool. The member and the attached ceramic substrate panels are then placed in a mold tool. When the mold tool is closed, it clamps down on the member around the ceramic substrate panel, and not on the ceramic substrate panel itself. A mold compound injected into the mold tool encapsulates the chips and ceramic substrate panels. Subsequently, packages each containing a chip are singulated from the encapsulated ceramic substrate panels.

Abstract: This invention provides a method for making a semiconductor package with stacked dies that substantially reduces risk of fracturing of the dies and prevents breakage of the wire bonds caused by wire sweep. One embodiment of the method includes the provision of a substrate and a pair of semiconductor dies, each having opposite top and bottom surfaces and a plurality of wire bonding pads around the peripheries of their respective top surfaces. One die is attached and wire bonded to a top surface of the substrate. A measured quantity of an uncured, fluid adhesive is dispensed onto the top surface of the first die, and the adhesive is squeezed out to the edges of the dies by pressing the bottom surface of the second die down onto the adhesive until the two dies are separated by a layer of the adhesive. The adhesive is cured and the second die is wire bonded to the substrate. A bead of an adhesive is dispensed around the periphery of the dies such that it covers the wire bonds and bonding pads on the second die.