Patents by Inventor Anthony J. McAuley

Anthony J. McAuley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120250529
    Abstract: In a mobile ad-hoc re-routing system in which network nodes are identified by topology dissemination messages, including local “Hello” and global Topographical Control (“TC”) messages, the improvement comprises triggering topology dissemination messages based on at least one of a new neighbor determination and link loss determinations.
    Type: Application
    Filed: May 27, 2010
    Publication date: October 4, 2012
    Inventors: John Lee, Subir Das, Anthony J. McAuley
  • Publication number: 20010036834
    Abstract: A method and system for fast intra-domain handoffs. In accordance with the method a mobility agent performs a duration limited multicast of packets destined for a mobile node to a well-defined set of subnet agents that form a multi-cast group. The well defined set includes the neighboring subnet agents of the subnet agent currently serving the mobile node. Once the multicast group is established the mobility agent then tunnels packets destined for the mobile node to each member of the multicast group. The members of the multicast group, i.e., the current subnet agent and its neighboring agents, then buffer the packets destined for the mobile node for a limited. When the mobile node then requests an IP address on the new subnet it is moving to, i.e., a local care-of address, the corresponding subnet agent then transmits the packets destined for the mobile node to the mobile node.
    Type: Application
    Filed: March 2, 2001
    Publication date: November 1, 2001
    Inventors: Subir Das, Ashutosh Dutta, Archan Misra, Anthony J. McAuley, Sajal K. Das
  • Patent number: 5930359
    Abstract: A system for a pipeline cascaded content addressable memory CAM system for sequentially processing input data includes an input register, a CAM core, cascade logic and an output register. As the memory association functions produce matches in the CAM core, the cascade logic in parallel composites data associated with each matching CAM core. Each cascade processes a separate data input simultaneously then passes on the cumulative results to the next stage.
    Type: Grant
    Filed: September 23, 1996
    Date of Patent: July 27, 1999
    Assignee: Motorola, Inc.
    Inventors: Robert Alan Kempke, Anthony J. McAuley, Michael P. Lamacchia
  • Patent number: 5841874
    Abstract: The present invention encompasses a method of storing ternary data that includes the steps of (1) initializing a conversion register by storing binary-to-ternary mask data in a conversion register; (2) storing ternary data in a content addressable memory (CAM) by inputting a single bit binary data to the conversion register, and converting the binary data into two bits of ternary data using the conversion register; and (3) simultaneously storing the two bits of ternary data in first and second memory cells. For subsequent searching, the method further includes the steps of searching for a match of input search binary data to the stored contents of the CAM; providing a match valid output responsive to the input search binary bits matching any of the stored contents; and generating an address corresponding to a location in the CAM where the match is found.
    Type: Grant
    Filed: August 13, 1996
    Date of Patent: November 24, 1998
    Assignee: Motorola, Inc.
    Inventors: Robert Alan Kempke, Anthony J. McAuley
  • Patent number: 5526370
    Abstract: A new class of error detection codes has powerful error detection properties, as well as significant implementation advantages. The inventive error detection codes are used in communication protocols to protect transmitted data from corruption.
    Type: Grant
    Filed: April 4, 1994
    Date of Patent: June 11, 1996
    Assignee: Bell Communications Research, Inc.
    Inventor: Anthony J. McAuley
  • Patent number: 5469433
    Abstract: The present invention is generally directed to the transmission of data in various types of communication systems, including local area networks (LANs) and wide area networks (WANs). A main object of the present invention is to provide a system based on a parallel structure that can assemble and disassemble packet information in constant time, no matter how corrupted, out of order, or duplicated the arriving packets. A further object of the present invention is to provide a system that would improve efficiency in broadband networks, particularly if implemented in a VLSI chip using the low complexity architecture-and-reassembly of the present invention.
    Type: Grant
    Filed: April 29, 1994
    Date of Patent: November 21, 1995
    Assignee: Bell Communications Research, Inc.
    Inventor: Anthony J. McAuley
  • Patent number: 5386413
    Abstract: A switch memory 100 for implementing a multilevel hierarchical routing table in a switch is disclosed. The switch memory 100 includes a plurality of mask circuits 120, 121 and 122, which each correspond to one level of the multilevel hierarchy. Each mask circuit 120, 121 and 122 receives a destination address of an incoming call or packet and masks out portions of the received destination address which do not correspond to the level of the hierarchy with which the mask circuit 120, 121 or 122 is associated. A memory array 130, 131 or 132 corresponding to each mask circuit 120, 121 or 122, is provided which is capable of storing a table of entries including an output port entry and a corresponding destination address of one level of the multilevel hierarchy of destination addresses.
    Type: Grant
    Filed: March 19, 1993
    Date of Patent: January 31, 1995
    Assignee: Bell Communications Research, Inc.
    Inventors: Anthony J. McAuley, Paul F. Tsuchiya, Daniel V. Wilson
  • Patent number: 5115436
    Abstract: In accordance with an inventive FEC code, data is transmitted in codewords comprising n m-bit symbols. Of the n symbols, k symbols are known information symbols and h symbols are parity symbols for erasure correction. All of the symbols of the codeword are elements of a field of 2.sup.m integers which is closed with respect to addition and multiplication such as a Galois field. To determine the h parity symbols, an encoder circuit derives a matrix corresponding to a set of simultaneous equations in terms of the k known information symbols and the h parity symbols. This set of equations is then solved for the h parity symbols so that a codeword is transmitted comprising k known information symbols and h known parity symbols. At a decoder, the values of up to h erased symbols in the codeword may be reconstructed using a similar set of simultaneous equations.
    Type: Grant
    Filed: May 4, 1990
    Date of Patent: May 19, 1992
    Assignee: Bell Communications Research
    Inventor: Anthony J. McAuley