Abstract: Efficient implementation techniques of a low power mode, (i.e. L2 mode for ADSL2) for DSL transceivers are described. The techniques save memory space and reduce implementation complexity. A constellation mapper in a DSL transmitter determines the number of bits to be retrieved for an ith sub-carrier in the low power mode based on the number of bits allocated for this same sub-carrier in a normal transmission mode, (e.g. L0 mode in ADSL2) and a bit allocation threshold T. A constellation demapper in a DSL receiver determines the number of bits used for an ith sub-carrier in the low power mode based on the bit tables for the L0 mode and the bit threshold T.

Abstract: A bi-level framing structure for DSL phone systems uses 4 KHz physical frames and mux data frames. The mux data frames each start with a sync byte and contain user payload bytes. A group of mux data frames are appended with forward-error-correction FEC bytes to make a codeword. The codeword is then partitioned into physical 4-KHz frames. The physical frames are transformed by an inverse fast-Fourier transform (IFFT) outputting symbols at 4 KHz for transmission. For high line rates, each codeword has S mux data frames and S physical frames. There are also at least S FEC bytes if error correction is enabled. However, for lower line rates, there are S physical frames but only S/M mux data frames in each codeword. The efficiency factor M is 1 for high line rates, but 4 for lower line rates. Reducing the number of mux data frames reduces the number of sync bytes in a codeword, decreasing overhead. The FEC bytes are spread among more physical frames, reducing error-correction overhead.

Abstract: A Digital-Subscriber Line (DSL) modem dynamically allocates bandwidth among one or more voice calls and unchannelized data, as needed. The channelized voice and unchannelized data traffic are transmitted over a digital subscriber line according to the bandwidth allocations therefor.

Abstract: A Digital-Subscriber Line (DSL) modem dynamically allocates its bandwidth to voice calls or data traffic as needed. Low-level frames are divided into several 64-Kbit/sec timeslots, each able to carry one voice call. These low-level frames are repeated several times in a 1-KHz frame that is synchronized to network timing references such as an 8-KHz clock used by the telephone network's pulse-code-modulated (PCM) highway. The 1-KHz frames are grouped into superframes. The low-level timeslots are allocated to either voice channels or to unchannelized data, depending on the number of voice calls currently being made. Allocations are made once for each superframe. The allocations or assignment of each of the timeslots to either voice or data is determined and sent to the remote modem or line card before the next superframe begins. When a good CRC occurs, the allocation sent is used to format the next superframe. Allocation bits for each of the timeslots indicate that the timeslot is for voice or for data.

Abstract: Pulp-insulated telephone cables common in Japan and other countries have higher cross-talk interference than plastic-insulated cables common in the United States. Deployment of newer xDSL systems in Japan has been limited by the high cross-talk interference in those pulp cables, especially the near-end cross-talk (NEXT) from ISDN services using time-compression multiplexing (TCM). A TCM-DSL that can share pulp-cable bundles with TCM ISDN lines eliminates the NEXT interference by synchronizing transmission and reception with the TCM ISDN equipment for the same cable bundle. The TCM-DSL line uses TCM that is synchronized with the ISDN transmit and receive windows so that the TCM-DSL is transmitting but not receiving when the ISDN modems at the same side are transmitting. When ISDN at the same side are receiving and not transmitting, NEXT interference does not exist. Thus higher-speed TCM-DSL data can be received during the ISDN receive windows with reduced interference.

Abstract: An integrated line-card terminates an asymmetric digital-subscriber line (ADSL) copper-pair at a single point in a central office. The line card contains analog line circuitry such as a ring generator, off-hook detector, D.C. current feed, and a single analog-digital (A/D) converter. The phone line carries a composite signal of both the high-frequency ADSL data and the low-frequency voice or plain-old-telephone-service (POTS) signal. Instead of using an analog frequency-splitter with bulky, expensive inductor coils, a digital splitter is used. A digital-signal processor (DSP) can be used to perform the digital splitting of ADSL and POTS. The waveforms from the analog phone line are first converted to digital values by the A/D converter, and then a digital splitter separates the low-frequency POTS from the high-frequency ADSL.

Abstract: A method and apparatus of managing a multi-channel direct memory access (DMA) operation in which descriptors of data buffers are stored in a circular descriptor queue. The descriptors of those data buffers that are currently available for use in a DMA transfer are maintained in contiguous locations in the descriptor queue. The location of the first available descriptor and the number of currently available descriptors in the descriptor queue are provided to a network controller. Based on this information, the network controller then obtains a set of available descriptors and fills the corresponding buffers with data as it arrives on the different channels. When the use of a data buffer in a DMA transfer is complete, the descriptor for this buffer is made available again in the descriptor queue by re-filling this descriptor immediately following the available descriptors.

Abstract: A method and apparatus of managing a multi-channel direct memory access (DMA) operation in which a sequence of data frames are received at a controller that controls a DMA transfer. The data frames are placed in data buffers in a memory by the controller. Multiple data frames are stored by the controller in at least one of the data buffers. The storing of multiple data frames in a single buffer provides efficient utilization of memory space as large size buffers are used to hold more than a single data frame, and also reduces the management overhead involved in placing the data frames in the data buffers.

Abstract: A combined BAUD rate generator and digital phase locked loop (DPLL) circuit operates in either an asynchronous BAUD rate generating mode or a synchronous phase-locked mode. The combination circuit requires less circuitry than a functionally equivalent circuit with a separate BAUD rate generator and DPLL. The combination circuit comprises a count register, a period register, a decrementing/incrementing circuit, a phase adjusting circuit, and a clock option register. In a first operating mode, the combination circuit functions as a programmable BAUD rate generator which may be used for asynchronous communication applications. In a second operating mode, the combination circuit functions as both a programmable BAUD rate generator and a digital phase locked loop that may be used for synchronous communication applications and that includes an improved method for phase locking a sampling signal to an input signal.

Abstract: A control system for a time division multiplex digital switching exchange has a number of telephony groups located on separate shelves which are interconnected by an intershelf bus. The intershelf bus comprises two address buses and a data bus. A common control computer inserts addressing data into two registers in a digital switch controller (DSC) which uses that data to control the transfer of data between telephony groups by way of the intershelf bus. The DSC also includes transmit and receive registers connected to the data bus which allows the transfer of data to and from the shelves and the common control computer. Should the common control computer require to read data from the DSC it addresses the DSC as one of the shelves (i.e., inserts the address of the DSC in the two registers of the DSC) to cause the DSC to transfer or read data to or from the transmit and receive register.