Abstract: Multiple data wordlengths may be supported by a processor through a single data path and/or a single set of registers. For example, the processor may support 16-bit wordlengths and 24-bit wordlengths through a single datapath. For supported data wordlengths that are less than the wordlength of the registers and datapath, the data may be left-aligned within the registers and datapath. The left alignment of data may allow saturation detection in the processor to be performed by examining the same saturation point regardless of the wordlength of the data being operated on. A special saturation mode of the processor may set the lower bits to zero when a configuration register or instruction-bit is set and saturation is detected.

Abstract: Accessing a circular buffer in memory from a processor may be performed with the aid of precomputed values stored in a pointer descriptor field of a processor storage element, such as a register. The pointer descriptor may store a precomputed value for calculating a memory address in the circular buffer, which may include two values, in which the two values are based, at least in part, on the size of the circular buffer, but neither be the size of the circular buffer. The first value may be used to derive a starting memory location for a circular buffer. The second value may be used in combination with the first value to calculate an end memory location. The start and end locations or addresses, along with the precomputed stored values, are then used to calculate the next address based on the current address of a circular buffer in an efficient manner.

Abstract: There is provided a noise cancellation system, comprising: an input for a digital signal, the digital signal having a first sample rate; a digital filter, connected to the input to receive the digital signal; a decimator, connected to the input to receive the digital signal and to generate a decimated signal at a second sample rate lower than the first sample rate; and a processor. The processor comprises: an emulation of the digital filter, connected to receive the decimated signal and to generate an emulated filter output; and a control circuit, for generating a control signal on the basis of the emulated filter output. The control signal is applied to the digital filter to control a filter characteristic thereof.

Abstract: A noise cancellation system for an audio system such as a mobile phone handset, or a wireless phone headset has a first input for receiving a first audio signal from one or more microphone positioned to receive ambient noise, and a second input for receiving a second audio signal from a microphone positioned to detect the user's speech, as well as a third input for receiving a third audio signal for example representing the speech of a person to whom the user is talking. A first noise cancellation block receives the first audio signal and generates a first noise cancellation signal, and this is combined with the third audio signal to form a first audio output signal. A second noise cancellation block receives at least a part of the first audio signal and said second audio signal and applying noise cancellation to generate a second audio output signal.

Abstract: An infinite impulse response (IIR) filter is provided for receiving an input signal and outputting a filtered signal. The filter comprises feedback circuitry for feeding back said filtered signal, the feedback circuitry comprising a first delay element for delaying said filtered signal; and a sub-unit, for receiving said delayed filtered signal, for outputting a summed signal which is the difference between said delayed filtered signal and a further-delayed filtered signal, and for outputting a multiplied signal which is an inverted further-delayed filtered signal multiplied by a first filter coefficient. At least said input signal, said delayed filtered signal, said multiplied signal, and said summed signal are employed to generate said filtered signal.

Abstract: A circuit for preventing clipping in an Automatic Level Control (ALC) or Limiter, where the amplitude of the signal above the clipping point is estimated, then the signal level is automatically reduced over a defined period substantially equal to the feedforward delay in the ALC/Limiter. By adaptively controlling, based on the excess amplitude and the delay time available, an attack rate used in the ALC/Limiter to reduce the gain applied to an input signal, it can be ensured that the output amplitude is brought within the clipping level sufficiently quickly to prevent audible clipping.

Abstract: An amplifier circuit (100) has an input stage (OP1) and an output stage (Q1, Q2) operating with different supply voltages and different quiescent voltages. The output stage has a feedback input connected to receive a feedback signal from the output of the output stage. A biasing circuit (602) applies a bias signal (Ioff) to said input stage at an operating level appropriate to establish a quiescent output voltage different from a ground reference level of the input stage.

Abstract: A noise cancellation system for an audio system such as a mobile phone handset, or a wireless phone headset has a first input for receiving a first audio signal from one or more microphone positioned to receive ambient noise, and a second input for receiving a second audio signal from a microphone positioned to detect the user?s speech, as well as a third input for receiving a third audio signal for example representing the speech of a person to whom the user is talking. A first noise cancellation block receives the first audio signal and generates a first noise cancellation signal, and this is combined with the third audio signal to form a first audio output signal. A second noise cancellation block receives at least a part of the first audio signal and said second audio signal and applying noise cancellation to generate a second audio output signal.

Abstract: There is provided a noise cancellation system, comprising: an input for a digital signal, the digital signal having a first sample rate; a digital filter, connected to the input to receive the digital signal; a decimator, connected to the input to receive the digital signal and to generate a decimated signal at a second sample rate lower than the first sample rate; and a processor. The processor comprises: an emulation of the digital filter, connected to receive the decimated signal and to generate an emulated filter output; and a control circuit, for generating a control signal on the basis of the emulated filter output. The control signal is applied to the digital filter to control a filter characteristic thereof.

Abstract: An infinite impulse response (IIR) filter is provided for receiving an input signal and outputting a filtered signal. The filter comprises feedback circuitry for feeding back said filtered signal, the feedback circuitry comprising a first delay element for delaying said filtered signal; and a sub-unit, for receiving said delayed filtered signal, for outputting a summed signal which is the difference between said delayed filtered signal and a further-delayed filtered signal, and for outputting a multiplied signal which is an inverted further-delayed filtered signal multiplied by a first filter coefficient. At least said input signal, said delayed filtered signal, said multiplied signal, and said summed signal are employed to generate said filtered signal.

Abstract: A circuit for preventing clipping in an Automatic Level Control (ALC) or Limiter, where the amplitude of the signal above the clipping point is estimated, then the signal level is automatically reduced over a defined period substantially equal to the feedforward delay in the ALC/Limiter. By adaptively controlling, based on the excess amplitude and the delay time available, an attack rate used in the ALC/Limiter to reduce the gain applied to an input signal, it can be ensured that the output amplitude is brought within the clipping level sufficiently quickly to prevent audible clipping.

Abstract: In a dynamic element matching stage of a digital-to-analogue converter, in which a pair of quantizer outputs are generated, and are constrained such that their sum is equal to the parity of a received bit value, steps are taken to improve baseband noise performance. Each of the quantizers has a feedback loop associated with it, and the performance is improved by determining the quantizer outputs based on these loop values, in order to reduce the overall quantization noise. However, during time periods when these loop values are equal, there are two possible pairs of quantizer outputs that could be chosen, without adversely impacting on the overall quantization noise. the quantizer outputs are monitored during such time periods, and steps are taken to control the quantizer outputs during such time periods, in order to ensure that the two possible pairs of quantizer outputs are chosen with equal probability.

Abstract: A sound reproduction device includes a filter, which detects a repeated bit sequence of a predetermined length in an input bit stream. When any repeated bit sequence having the predetermined length is detected, the input bit stream is applied to a filter for attenuating signals at the frequency corresponding to the predetermined length.

Abstract: In a dynamic element matching stage of a digital-to-analogue converter, in which a pair of quantizer outputs are generated, and are constrained such that their sum is equal to the parity of a received bit value, steps are taken to improve baseband noise performance. Each of the quantizers has a feedback loop associated with it, and the performance is improved by determining the quantizer outputs based on these loop values, in order to reduce the overall quantization noise. However, during time periods when these loop values are equal, there are two possible pairs of quantizer outputs that could be chosen, without adversely impacting on the overall quantization noise. the quantizer outputs are monitored during such time periods, and steps are taken to control the quantizer outputs during such time periods, in order to ensure that the two possible pairs of quantizer outputs are chosen with equal probability.

Abstract: A feedback controller in a PWM amplifier comprises a signal input for receiving a pulse width modulated (PWM) input signal (Vin) whose duty cycle represents a desired analogue output signal. A feedback loop filter 518 generates a filtered error signal (Vint) comprising a filtered representation of differences between the input signal (Vin) and a feedback signal (Vfb). A comparator (520) compares the filtered error signal with a reference to generate a provisional PWM switching control signal (C) for controlling the PWM amplifier (500). A pulse conditioner (532) receives both the provisional PWM switching control signal (C) and the PWM input signal (X=Vin) and outputs to the amplifier (500) a conditioned PWM switching control signal (Y), modified in accordance with predetermined constraints in relation to the PWM input signal.

Abstract: An amplifier circuit (100) has an input stage (OP1) and an output stage (Q1, Q2) operating with different supply voltages and different quiescent voltages. The output stage has a feedback input connected to receive a feedback signal from the output of the output stage. A biasing circuit (602) applies a bias signal (Ioff) to said input stage at an operating level appropriate to establish a quiescent output voltage different from a ground reference level of the input stage.