Abstract: Hybrid parallelized tagged geometric (TAGE) branch prediction, including: selecting, based on a branch instruction, a first plurality of counts from at least one TAGE table; selecting, based on the branch instruction, a second plurality of counts from at least one non-TAGE branch prediction table; generating, based on the first plurality of counts and a second plurality of counts; and wherein selecting the first plurality of counts and selecting the second plurality of counts are performed during a same branch prediction pipeline stage.

Abstract: Enforcing consistency across redundant tagged geometric (TAGE) branch histories, including: determining, by a TAGE branch predictor, whether a predefined interval has occurred; and storing, in a retirement branch history, in response to the predefined interval occurring, a copy of a global branch history.

Abstract: A tagged geometric (TAGE) branch predictor for managing large TAGE branch histories, including: logic that maintains a global branch history including a circular buffer; logic that maintains a plurality of TAGE tables; and logic that maintains a plurality of folded branch histories, wherein each folded branch history of the plurality of folded branch histories corresponds to a TAGE table of the plurality of TAGE tables, wherein the folded branch histories are each based on different length subsets of the global branch history.

Abstract: A processor includes two or more branch target buffer (BTB) tables for branch prediction, each BTB table storing entries of a different target size or width or storing entries of a different branch type. Each BTB entry includes at least a tag and a target address. For certain branch types that only require a few target address bits, the respective BTB tables are narrower thereby allowing for more BTB entries in the processor separated into respective BTB tables by branch instruction type. An increased number of available BTB entries are stored in a same or a less space in the processor thereby increasing a speed of instruction processing. BTB tables can be defined that do not store any target address and rely on a decode unit to provide it. High value BTB entries have dedicated storage and are therefore less likely to be evicted than low value BTB entries.

Abstract: A processor predicts a number of loop iterations associated with a set of loop instructions. In response to the predicted number of loop iterations exceeding a first loop iteration threshold, the set of loop instructions are executed in a loop mode that includes placing at least one component of an instruction pipeline of the processor in a low-power mode or state and executing the set of loop instructions from a loop buffer. In response to the predicted number of loop iterations being less than or equal to a second loop iteration threshold, the set of instructions are executed in a non-loop mode that includes maintaining at least one component of the instruction pipeline in a powered up state and executing the set of loop instructions from an instruction fetch unit of the instruction pipeline.

Abstract: A processor includes a prediction engine coupled to a training engine. The prediction engine includes a loop exit predictor. The training engine includes a loop exit branch monitor coupled to a loop detector. Based on at least one of a plurality of call return levels, the loop detector of the processor takes a snapshot of a retired predicted block during a first retirement time, compares the snapshot to a subsequent retired predicted block at a second retirement time, and based on the comparison, identifies a loop and loop exit branches within the loop for use by the loop exit branch monitor and the loop exit predictor to determine whether to override a general purpose conditional prediction.

Abstract: Merging branch target buffer entries includes maintaining, in a branch target buffer, an entry corresponding to first branch instruction, where the entry identifies a first branch target address for the first branch instruction and a second branch target address for a second branch instruction; and accessing, based on the first branch instruction, the entry.

Abstract: A processor predicts a number of loop iterations associated with a set of loop instructions. In response to the predicted number of loop iterations exceeding a first loop iteration threshold, the set of loop instructions are executed in a loop mode that includes placing at least one component of an instruction pipeline of the processor in a low-power mode or state and executing the set of loop instructions from a loop buffer. In response to the predicted number of loop iterations being less than or equal to a second loop iteration threshold, the set of instructions are executed in a non-loop mode that includes maintaining at least one component of the instruction pipeline in a powered up state and executing the set of loop instructions from an instruction fetch unit of the instruction pipeline.

Abstract: A metal working fluid having increased resistance to bacterial growth. The metal working fluid includes a cross-linked polymeric ester emulsifier; and an amine represented by the formula (H2N)a-Q-(NH2)b, where a and b are each integers, and Q is at least one carbon atom. Q may also be represented by X—Y—Z, where a+b?2; X is a cyclic ring system including 3 to 24 carbon atoms; and Y and Z are groups that include at least one carbon atom directly attached to the cyclic ring system. The metal working fluid may also include a biocide, and may also include an amide that is formed by reacting the amine with a carboxylic acid.

Abstract: A processor predicts a number of loop iterations associated with a set of loop instructions. In response to the predicted number of loop iterations exceeding a first loop iteration threshold, the set of loop instructions are executed in a loop mode that includes placing at least one component of an instruction pipeline of the processor in a low-power mode or state and executing the set of loop instructions from a loop buffer. In response to the predicted number of loop iterations being less than or equal to a second loop iteration threshold, the set of instructions are executed in a non-loop mode that includes maintaining at least one component of the instruction pipeline in a powered up state and executing the set of loop instructions from an instruction fetch unit of the instruction pipeline.

Abstract: A metal working fluid having increased resistance to bacterial growth. The metal working fluid includes a cross-linked polymeric ester emulsifier; and an amine represented by the formula (H2N)a-Q-(NH2)b, where a and b are each integers, and Q is at least one carbon atom. Q may also be represented by X—Y—Z, where a+b?2; X is a cyclic ring system including 3 to 24 carbon atoms; and Y and Z are groups that include at least one carbon atom directly attached to the cyclic ring system. The metal working fluid may also include a biocide, and may also include an amide that is formed by reacting the amine with a carboxylic acid.

Abstract: A processor includes two or more branch target buffer (BTB) tables for branch prediction, each BTB table storing entries of a different target size or width or storing entries of a different branch type. Each BTB entry includes at least a tag and a target address. For certain branch types that only require a few target address bits, the respective BTB tables are narrower thereby allowing for more BTB entries in the processor separated into respective BTB tables by branch instruction type. An increased number of available BTB entries are stored in a same or a less space in the processor thereby increasing a speed of instruction processing. BTB tables can be defined that do not store any target address and rely on a decode unit to provide it. High value BTB entries have dedicated storage and are therefore less likely to be evicted than low value BTB entries.

Abstract: A processor includes two or more branch target buffer (BTB) tables for branch prediction, each BTB table storing entries of a different target size or width or storing entries of a different branch type. Each BTB entry includes at least a tag and a target address. For certain branch types that only require a few target address bits, the respective BTB tables are narrower thereby allowing for more BTB entries in the processor separated into respective BTB tables by branch instruction type. An increased number of available BTB entries are stored in a same or a less space in the processor thereby increasing a speed of instruction processing. BTB tables can be defined that do not store any target address and rely on a decode unit to provide it. High value BTB entries have dedicated storage and are therefore less likely to be evicted than low value BTB entries.

Abstract: The present invention is in the field of frozen compositions. In particular, the invention relates to frozen compositions of the water ice type. The invention provides frozen confections comprising water, a freezing point depressant and defibrillated primary cell wall material comprising microfibrils. The invention also relates to a method for preparing a frozen confection comprising water, a freezing point depressant and defibrillated primary cell wall material comprising microfibrils, wherein the method includes a high shear treatment step.

Abstract: A processor includes a prediction engine coupled to a training engine. The prediction engine includes a loop exit predictor. The training engine includes a loop exit branch monitor coupled to a loop detector. Based on at least one of a plurality of call return levels, the loop detector of the processor takes a snapshot of a retired predicted block during a first retirement time, compares the snapshot to a subsequent retired predicted block at a second retirement time, and based on the comparison, identifies a loop and loop exit branches within the loop for use by the loop exit branch monitor and the loop exit predictor to determine whether to override a general purpose conditional prediction.

Abstract: Methods of increasing the particle size of ammonium octamolybdate (AOM) pigment powder are provided. A method can include heating the AOM pigment powder to a temperature above 20° C. for a given amount of time. An ink composition can be produced by formulating AOM pigment powder with increased particle size and incorporating the AOM pigment powder into an ink composition.

Abstract: Systems and methods selectively filter, buffer, and process cache coherency probes. A processor includes a probe buffering unit that includes a cache coherency probe buffer. The probe buffering unit receives cache coherency probes and memory access requests for a cache. The probe buffering unit identifies and discards any of the probes that are directed to a memory block that is not cached in the cache, and buffers at least a subset of the remaining probes in the probe buffer. The probe buffering unit submits to the cache, in descending order of priority, one or more of: any buffered probes that are directed to the memory block to which a current memory access request is also directed; any current memory access requests that are directed to a memory block to which there is not a buffered probe also directed; and any buffered probes when there is not a current memory access request.

Abstract: A processor includes two or more branch target buffer (BTB) tables for branch prediction, each BTB table storing entries of a different target size or width or storing entries of a different branch type. Each BTB entry includes at least a tag and a target address. For certain branch types that only require a few target address bits, the respective BTB tables are narrower thereby allowing for more BTB entries in the processor separated into respective BTB tables by branch instruction type. An increased number of available BTB entries are stored in a same or a less space in the processor thereby increasing a speed of instruction processing. BTB tables can be defined that do not store any target address and rely on a decode unit to provide it. High value BTB entries have dedicated storage and are therefore less likely to be evicted than low value BTB entries.

Abstract: The present disclosure relates to emulsifying agents produced from succinic acids or anhydrides and polyalkylene glycols. The present disclosure also relates to lubricating oils containing such emulsifying agents. The emulsifying agent provides a lubricating oil that is substantially free of an aqueous layer after about 24 hours when tested according to ASTM D7563-10.