Patents by Inventor Anthony Jebson
Anthony Jebson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10019394Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.Type: GrantFiled: March 21, 2017Date of Patent: July 10, 2018Assignee: ARM LimitedInventors: Michael Alexander Kennedy, Anthony Jebson
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Publication number: 20170192915Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.Type: ApplicationFiled: March 21, 2017Publication date: July 6, 2017Inventors: Michael Alexander KENNEDY, Anthony JEBSON
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Patent number: 9632957Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.Type: GrantFiled: April 24, 2015Date of Patent: April 25, 2017Assignee: ARM LimitedInventors: Michael Alexander Kennedy, Anthony Jebson
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Patent number: 9378162Abstract: An interrupt controller for controlling the routing and handling of interrupts received at a data processing apparatus including at least one physical processing unit configured to run at least one of a plurality of virtual processors and a memory. The interrupt controller includes redistribution circuitry with at least one data store corresponding to the unit, the data store storing a pointer to a virtual pending table storing currently pending virtual interrupts for a virtual processor currently running on the corresponding unit and a pointer to a pending table configured to store currently pending physical interrupts for the corresponding unit and an input configured to receive a virtual interrupt for interrupting a virtual processor. Control circuitry is configured to add the virtual interrupt to the virtual pending table and to store the virtual interrupt in the virtual pending table for the virtual processor that is stored in the memory.Type: GrantFiled: May 21, 2013Date of Patent: June 28, 2016Assignee: ARM LimitedInventors: Anthony Jebson, Andrew John Turner, Matthew Lucien Evans, Gareth James Evans, Adam James McNeeney
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Patent number: 9330035Abstract: A data processing device comprises a plurality of system registers and a set of interrupt handling registers for controlling handling of an incoming interrupt. The device also includes processing circuitry configured to execute software of the plurality of execution levels, and interrupt controller circuitry configured to route said incoming interrupts to interrupt handling software that is configured to run at one of said plurality of execution levels, and register access control circuitry configured to dynamically control access to at least some of said interrupt handling registers in dependence upon one of said plurality of execution levels that said incoming interrupt is routed to. The interrupt handling software configured to run at a particular execution level does not have access to interrupt handling registers for handling a different incoming interrupt that is routed to interrupt handling software that is configured to run at a more privileged execution level.Type: GrantFiled: May 23, 2013Date of Patent: May 3, 2016Assignee: ARM LimitedInventors: Anthony Jebson, Richard Roy Grisenthwaite, Michael Alexander Kennedy, Ian Michael Caulfield
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Publication number: 20150227477Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.Type: ApplicationFiled: April 24, 2015Publication date: August 13, 2015Inventors: Michael Alexander Kennedy, Anthony Jebson
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Patent number: 9043522Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.Type: GrantFiled: October 17, 2012Date of Patent: May 26, 2015Assignee: ARM LimitedInventors: Michael Alexander Kennedy, Anthony Jebson
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Patent number: 8924615Abstract: A global interrupt number space 38 is provided for use in message signalled interrupts. Interrupt destinations 10, 12, 14, 16 are provided with pending interrupt caches 24 with either backing storage provided by global pending status memory 34 shared by all the caches or separate individual pending status memories 56. The interrupt number space may be divided into regions with programmable mapping data being used to indicate which interrupt destinations are responsible for which regions. When interrupts are migrated from one interrupt destination to another, then such programmable mapping data is updated. Pending interrupts may be flushed back to the global pending status memory 34 during the reassignment process such that this pending interrupt data may be picked up by the newly responsible interrupt destination.Type: GrantFiled: October 26, 2012Date of Patent: December 30, 2014Assignee: ARM LimitedInventors: Richard Roy Grisenthwaite, Anthony Jebson, Andrew Christopher Rose, Matthew Lucien Evans
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Publication number: 20140351471Abstract: An interrupt controller for controlling the routing and handling of interrupts received at a data processing apparatus including at least one physical processing unit configured to run at least one of a plurality of virtual processors and a memory. The interrupt controller includes redistribution circuitry with at least one data store corresponding to the unit, the data store storing a pointer to a virtual pending table storing currently pending virtual interrupts for a virtual processor currently running on the corresponding unit and a pointer to a pending table configured to store currently pending physical interrupts for the corresponding unit and an input configured to receive a virtual interrupt for interrupting a virtual processor. Control circuitry is configured to add the virtual interrupt to the virtual pending table and to store the virtual interrupt in the virtual pending table for the virtual processor that is stored in the memory.Type: ApplicationFiled: May 21, 2013Publication date: November 27, 2014Inventors: Anthony JEBSON, Andrew John TURNER, Matthew Lucien EVANS, Gareth James EVANS, Adam James MCNEENEY
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Publication number: 20140351472Abstract: A data processing device comprises a plurality of system registers and a set of interrupt handling registers for controlling handling of an incoming interrupt. The device also includes processing circuitry configured to execute software of the plurality of execution levels, and interrupt controller circuitry configured to route said incoming interrupts to interrupt handling software that is configured to run at one of said plurality of execution levels, and register access control circuitry configured to dynamically control access to at least some of said interrupt handling registers in dependence upon one of said plurality of execution levels that said incoming interrupt is routed to. The interrupt handling software configured to run at a particular execution level does not have access to interrupt handling registers for handling a different incoming interrupt that is routed to interrupt handling software that is configured to run at a more privileged execution level.Type: ApplicationFiled: May 23, 2013Publication date: November 27, 2014Applicant: ARM LIMITEDInventors: Anthony JEBSON, Richard Roy GRISENTHWAITE, Michael Alexander KENNEDY, Ian Michael CAULFIELD
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Publication number: 20140122760Abstract: A global interrupt number space 38 is provided for use in message signalled interrupts. Interrupt destinations 10, 12, 14, 16 are provided with pending interrupt caches 24 with either backing storage provided by global pending status memory 34 shared by all the caches or separate individual pending status memories 56. The interrupt number space may be divided into regions with programmable mapping data being used to indicate which interrupt destinations are responsible for which regions. When interrupts are migrated from one interrupt destination to another, then such programmable mapping data is updated. Pending interrupts may be flushed back to the global pending status memory 34 during the reassignment process such that this pending interrupt data may be picked up by the newly responsible interrupt destination.Type: ApplicationFiled: October 26, 2012Publication date: May 1, 2014Applicant: ARM LimitedInventors: Richard Roy GRISENTHWAITE, Anthony JEBSON, Andrew Christopher ROSE, Matthew Lucien EVANS
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Publication number: 20140108691Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.Type: ApplicationFiled: October 17, 2012Publication date: April 17, 2014Applicant: ARM LIMITEDInventors: Michael Alexander KENNEDY, Anthony JEBSON
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Patent number: 7290254Abstract: In one embodiment of the present invention, a method includes translating instructions of a code portion from a first instruction set to a native instruction set; and disabling of translating the instructions when a compilation process is ready for execution.Type: GrantFiled: March 25, 2003Date of Patent: October 30, 2007Assignee: Intel CorporationInventors: Lynn A. Comp, Anthony Jebson
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Patent number: 7107305Abstract: A tightly coupled dual 16-bit multiply-accumulate (MAC) unit for performing single-instruction/multiple-data (SIMD) operations may forward an intermediate result to another operation in a pipeline to resolve an accumulating dependency penalty. The MAC unit may also be used to perform 32-bit×32-bit operations.Type: GrantFiled: October 5, 2001Date of Patent: September 12, 2006Assignee: Intel CorporationInventors: Deli Deng, Anthony Jebson, Yuyun Liao, Nigel C. Paver, Steve J. Strazdus
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Patent number: 6986023Abstract: A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.Type: GrantFiled: August 9, 2002Date of Patent: January 10, 2006Assignee: Intel CorporationInventors: Nigel C. Paver, William T. Maghielse, Wing K. Yu, Jianwei Liu, Anthony Jebson, Kailesh B. Bavaria, Rupal M. Parikh, Deli Deng, Mukesh Patel, Mark Fullerton, Murli Ganeshan, Stephen J. Strazdus
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Publication number: 20040194076Abstract: In one embodiment of the present invention, a method includes translating instructions of a code portion from a first instruction set to a native instruction set; and disabling of translating the instructions when a compilation process is ready for execution.Type: ApplicationFiled: March 25, 2003Publication date: September 30, 2004Inventors: Lynn A. Comp, Anthony Jebson
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Publication number: 20040030862Abstract: A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.Type: ApplicationFiled: August 9, 2002Publication date: February 12, 2004Inventors: Nigel C. Paver, William T. Maghielse, Wing K. Yu, Jianwei Liu, Anthony Jebson, Kailesh B. Bavaria, Rupal M. Parikh, Deli Deng, Mukesh Patel, Mark Fullerton, Murli Ganeshan, Stephen J. Strazdus
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Publication number: 20030069913Abstract: A tightly coupled dual 16-bit multiply-accumulate (MAC) unit for performing single-instruction/multiple-data (SIMD) operations may forward an intermediate result to another operation in a pipeline to resolve an accumulating dependency penalty. The MAC unit may also be used to perform 32-bit×32-bit operations.Type: ApplicationFiled: October 5, 2001Publication date: April 10, 2003Inventors: Deli Deng, Anthony Jebson, Yuyun Liao, Nigel C. Paver, Steve J. Strazdus