Abstract: A digital system has a main memory 10 with a main memory access (DMA) unit 11 through which data channels 12, 13 are coupled to the memory. A processor system (processor 14, RAM data memory 15, instruction memory 16) is also coupled to the memory through a read/write buffer 20, each read stalling the processor for typically 5 cycles. For block reads, a block memory read unit 25 is connected in parallel with the path between the read/write buffer 20 and the DMA unit 11. This block read unit can be set from the processor 14 with a block start address and a block length passed as writes through the read/write buffer 20. The block is read (first phase) word by word from the main memory via the DMA unit into a memory 28 in the block read unit.