Abstract: An improved power-up circuit for exerting control over output buffer devices in such a way as to disable these buffer devices during the period when the extended circuit is vulnerable to transient effects as the common power supply voltage V.sub.cc is rising during the "power-up" or "power-down" of the extended circuit. One particular such transient effect is the loading down of the power supply due to the buffer devices being in the current-sourcing and in the current-sinking states simultaneously. One improvement over the earlier circuitry is the provision of an asymmetry in the values of V.sub.cc at which control is transferred between the power-up circuit and the rest of the circuit as V.sub.cc is rising during power-up and as V.sub.cc is falling during power-down, respectively. In particular, the design of the present circuit allows control to be exerted over the buffer devices up to a relatively high value of V.sub.