Abstract: A computing device includes an appliance status table to store at least one of reliability and performance data for one or more network functions virtualization (NFV) appliances and one or more legacy network appliances. The computing device includes a load controller to configure an Internet Protocol (IP) filter rule to select a packet for which processing of the packet is to be migrated from a selected one of the one or more legacy network appliances to a selected one of the one or more NFV appliances, and to update the appliance status table with received at least one of reliability and performance data for the one or more legacy network appliances and the one or more NFV appliances. The computing device includes a packet distributor to receive the packet, to select one of the one or more NFV appliances based at least in part on the appliance status table, and to send the packet to the selected NFV appliance. Other embodiments are described herein.

Abstract: Methods and apparatus, including computer program products, are provided for express voting. In some example embodiments, there is provided a method for express voting. The method may include authenticating a voter based on a token carried by a user equipment, the token mapped to at least one of an identity of the voter, a precinct of the voter, and a ballot for the voter; and providing, when the authenticating indicates the voter is authorized to vote, the ballot presented on the user equipment. Related systems, methods, and articles of manufacture are also disclosed.

Abstract: Examples include techniques to monitor control plane (CP) network traffic. Examples include monitoring CP traffic between one or more user equipment (UEs) wirelessly coupled to a network and a virtual network function arranged to process user plane (UP) traffic for an application service provided to the one or more UEs to determine whether at least a portion of the UP traffic needs to be routed to a different VNF for UP processing.

Abstract: A power system that uses machine learning algorithms to solve various problems related to the delivery of power on integrated circuit systems is provided. The power system may process data on a platform near the target integrated circuit or off-platform in a cloud so that the machine learning algorithms can extract information from the data, process and analyze the data, and perform suitable action based on the analysis results. Applying machine learning to integrated circuit power delivery may involve the application of algorithms such as anomaly detection, load prediction, regression, and classification. Operated in this way, the power system may be provided with improved voltage/frequency scaling capabilities, security, and power efficiency.

Abstract: Methods and apparatus, including computer program products, are provided for express voting. In some example embodiments, there is provided a method for express voting. The method may include authenticating a voter based on a token carried by a user equipment, the token mapped to at least one of an identity of the voter, a precinct of the voter, and a ballot for the voter; and providing, when the authenticating indicates the voter is authorized to vote, the ballot presented on the user equipment. Related systems, methods, and articles of manufacture are also disclosed.

Abstract: An FPGA power management system includes a host power management integrated circuit connected to a system power control block of an FPGA via an FPGA configuration/monitoring bus and a computing device via a power configuration/monitoring bus. The host power management integrated circuit includes a configuration and monitoring block configured to communicate configuration/monitoring signals to and from the FPGA system power control block and the computing device. The host power management integrated circuit further includes at least one voltage regulator for supplying an output voltage to an FPGA power rail according to a power configuration signal communicated by the configuration and monitoring block. The host power management integrated circuit further includes a power profiler configured to measure and supply to the configuration and monitoring block an output current on the FPGA power rail.

Abstract: A controller is provided for controlling a power stage of a power converter according to a control law, the control law implementing a specific type of compensator and being pre-designed to generate an objective response of a default power converter for a default parameter value of a component of the power stage. The controller is further configured to determine an actual response for an actual parameter value of the component of the power stage and to alter the control law for the actual parameter value of the component of the power stage such that the actual response matches the objective response. The controller determines a degree of matching between the actual response and the objective response by filtering the actual response to generate a filtered actual response and integrating a product of the filtered actual response and a delayed actual response.

Abstract: In a control method for a power converter, an output voltage is generated according to a control law controlling a switched power stage. During ramp up of the power converter, at least one parameter of the power stage is identified, and the control law is adapted to the identified at least one parameter of the power stage for operating the power converter.

Abstract: A control method is provided for a power converter configured to generate an output voltage according to a control law controlling a power stage. The method comprises a dual stage identification process for identifying parameters of the power stage. The method includes, in a first stage, identifying at least one parameter of the power stage during ramp up of the power converter and adapting the control law to the identified at least one parameter of said power stage for operating the power converter. The method further includes, in a second stage, determining a response of the power stage; identifying at least one other parameter of the power stage by characterizing the response; and further adapting the control law according to a characteristic of the response.

Abstract: A controller of a power converter and related method pre-determine a range of suitable compensators across an end user's design space and permit the end user to configure the compensator such that the most suitable compensator is selected.

Abstract: The present application provides a tunable compensator providing a control signal to control a switch in a power supply. A measurement is taken of the level of activity of the control signal. This measurement is used to introduce a bias into a tuner tuning the compensator when the amount of activity in the control signal drops.

Abstract: A method for tuning a parameter of an electronic device includes: measuring a tuning variable x; and translating the measured tuning variable into a tuning range out of a plurality of tuning ranges representing a piece-wise tuning function. The piece-wise tuning function represents a tuning variable to parameter value mapping. Each tuning range i is associated with a nominal parameter value Mi. The method further includes determining a parameter value M within said tuning range, and setting the parameter to the determined parameter value.

Abstract: An electronic system, e.g. a power supply, includes elements, and the elements include devices that limit reliability of the electronic system. A system that can monitor parameters that affect electronic system reliability such as temperature, and parameters that can predict power supply failure such as bulk capacitor ESR, includes a monitoring system measuring and monitoring at least one reliability limiting parameter of at least one of the devices connected to the monitoring system. A method for estimating and predicting a failure of the electronic system includes: measuring parameters affecting or associating the reliability of the device by sensors, collecting the measured sensor data and/or other data by a communications unit, and communicating the data to a computing device for processing and predicting a failure of the device and alerting to the failure.

Abstract: A power converter includes a switched power stage configured to generate an output voltage from an input voltage and a controller configured to generate a pulsed control signal for switching the switched power stage in dependence upon a voltage error signal. The voltage error signal is a difference between a reference voltage and an output voltage. The controller comprises a digital pulse width modulation control path and a digital constant on-time control path. The controller is configured to toggle between a light load mode in which the digital constant-on-time control path is activated and a high load mode in which the digital PWM control path is activated. The constant-on time control path is designed digitally.

Abstract: An FPGA power management system includes a host power management integrated circuit connected to a system power control block of an FPGA via an FPGA configuration/monitoring bus and a computing device via a power configuration/monitoring bus. The host power management integrated circuit includes a configuration and monitoring block configured to communicate configuration/monitoring signals to and from the FPGA system power control block and the computing device. The host power management integrated circuit further includes at least one voltage regulator for supplying an output voltage to an FPGA power rail according to a power configuration signal communicated by the configuration and monitoring block. The host power management integrated circuit further includes a power profiler configured to measure and supply to the configuration and monitoring block an output current on the FPGA power rail.

Abstract: A controller is provided for controlling a power stage of a power converter according to a control law, the control law implementing a specific type of compensator and being pre-designed to generate an objective response of a default power converter for a default parameter value of a component of the power stage. The controller is further configured to determine an actual response for an actual parameter value of the component of the power stage and to alter the control law for the actual parameter value of the component of the power stage such that the actual response matches the objective response. The controller determines a degree of matching between the actual response and the objective response by filtering the actual response to generate a filtered actual response and integrating a product of the filtered actual response and a delayed actual response.

Abstract: A control method is provided for a power converter configured to generate an output voltage according to a control law controlling a power stage. The method comprises a dual stage identification process for identifying parameters of the power stage. The method includes, in a first stage, identifying at least one parameter of the power stage during ramp up of the power converter and adapting the control law to the identified at least one parameter of said power stage for operating the power converter. The method further includes, in a second stage, determining a response of the power stage; identifying at least one other parameter of the power stage by characterizing the response; and further adapting the control law according to a characteristic of the response.

Abstract: In a control method for a power converter, an output voltage is generated according to a control law controlling a switched power stage. During ramp up of the power converter, at least one parameter of the power stage is identified, and the control law is adapted to the identified at least one parameter of the power stage for operating the power converter.

Abstract: A current sense arrangement for switched power converters is provided wherein the clock used for sampling a sensed current of a power stage of the switched power converter is derived asynchronously from a master clock such that the local clock and the master clock are de-correlated. De-correlation can be achieved by deriving the local clock from the master clock with a modulo-m-counter having a sequence length.

Abstract: A system includes a plurality of DC-DC converters connected in parallel. Each DC-DC converter of the plurality of converters comprising an adaptive controller is configured to adaptively alter an output resistance of the DC-DC converter by adaptively altering a load line of the DC-DC converter such that a difference between each current being supplied by each DC-DC converter of the plurality of DC-DC converters into a common load is minimized.