Abstract: A structure and method of forming the structure. At least one copper wire is formed within a first dielectric layer of a substrate. The top surface of each copper wire and of the first dielectric layer are essentially coplanar. A recess is formed in the first dielectric layer from the top surface of each copper wire to a recess depth less than a thickness of each copper wire within the first dielectric layer such that the recess surrounds a perimeter surface of each copper wire. A capping layer, which is a copper diffusion barrier, is formed in the recess and on the top surface of each copper wire and on the first dielectric layer. A second dielectric layer is formed on the capping layer. The recess depth has a magnitude sufficient to prevent a lateral fail of the capping layer during packaging and/or operation of the substrate.

Abstract: The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing.

Abstract: A method for forming a vertical natural capacitor in an integrated circuit is disclosed. In one embodiment, the method includes forming a first set of concentric conductive annular structures in a first metal layer of an integrated circuit. The first set includes a first electrode and a second electrode. The method further includes forming a second set of concentric conductive annular structures in a second metal layer of the integrated circuit, the second set being substantially axially concentric with the first set. The second set also includes a first electrode and a second electrode. The method includes coupling, using conductive vias, the first electrode of the first set to the first electrode of the second set, and the second electrode of the first set to the second electrode of the second set.

Abstract: A semiconductor device having wiring levels on opposite sides, a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides, and a design structure of a semiconductor device having wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

Abstract: A method of reducing foreign material concentrations in an etch chamber having inner chamber walls is described. The method includes the step of etching a work piece in the etch chamber such that reaction products from the work piece having one or more elements form a first layer of reaction products that partially adhere to the inner chamber walls. A species is introduced into the etch chamber that increases the adhesion of the first layer of reaction products to the inner chamber walls.

Abstract: An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.

Abstract: A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by side wall spacers.

Abstract: An method of packaging an electronic device. The method for packaging the device including: providing a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.

Abstract: A method of a semiconductor device. A substrate is provided. At least one metal wiring level is within the substrate. An insulative layer is deposited on a surface of the substrate. An inductor is formed within the insulative layer using a patterned plate process. A wire bond pad is formed within the insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

Abstract: A semiconductor structure. The semiconductor structure includes: a substrate having at least one metal wiring level within the substrate; an insulative layer on a surface of the substrate; an inductor within the insulative layer; and a wire bond pad within the insulative layer. The inductor and the wire bond pad are substantially co-planar. The inductor has a height greater than a height of the wire bond pad.

Abstract: A method of forming a semiconductor substrate. A substrate is provided. At least one metal wiring level is within the substrate. A first insulative layer is deposited on a surface of the substrate. A portion of a wire bond pad is formed within the first insulative layer. A second insulative layer is deposited on the first insulative layer. An iductor is within the second insulative layer using a patterned plate process. A remaining portion of the wire bond pad is formed within the second insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

Abstract: A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above a top surface of the substrate; an insulative layer on and above a top surface of the capping layer; an inductor comprising a first portion in and above the insulative layer and a second portion only above the insulative layer; and a wire bond pad within the insulative layer, wherein the first portion the inductor has a height in a first direction greater than a height of the wire bond pad in the first direction, wherein the first direction is perpendicularly directed from the top surface of substrate toward the insulative layer.

Abstract: A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above the substrate; an insulative layer on and above the capping layer; a first layer of photo-imagable material on and above the insulative layer; a layer of oxide on and above the first layer of photo-imagable material; a second layer of photo-imagable material on and above the layer of oxide; an inductor; and a wire bond pad. A first portion of the inductor is in the second layer of photo-imagable material, the layer of oxide, the first layer of photo-imagable material, the insulative layer, and the capping layer. A second portion of the inductor is in only the second layer of photo-imagable material. The wire bond pad in only the first layer of photo-imagable material, the insulative layer, and the capping layer.

Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

Abstract: An integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive line segments being (i) directly above the first source/drain region and (ii) electrically coupled to the first source/drain region through first contact regions and second contact regions, respectively. The first and second electrically conductive line segments (i) reside in a first interconnect layer of the integrated circuit and (ii) run in the reference direction. The IC further includes an electrically conductive line being (i) directly above the first source/drain region, (ii) electrically coupled to the first and second electrically conductive line segments through a first via and a second via, respectively, (iii) resides in a second interconnect layer of the integrated circuit, and (iv) runs in the reference direction.

Abstract: A semiconductor structure and methods for forming the same. A semiconductor fabrication method includes steps of providing a structure. A structure includes (a) a dielectric layer, (b) a first electrically conductive region buried in the dielectric layer, wherein the first electrically conductive region comprises a first electrically conductive material, and (c) a second electrically conductive region buried in the dielectric layer, wherein the second electrically conductive region comprises a second electrically conductive material being different from the first electrically conductive material. The method further includes the steps of creating a first hole and a second hole in the dielectric layer resulting in the first and second electrically conductive regions being exposed to a surrounding ambient through the first and second holes, respectively. Then, the method further includes the steps of introducing a basic solvent to bottom walls and side walls of the first and second holes.

Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

Abstract: A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing in the ILD layer. The diffusion barrier region (i) physically isolates, (ii) electrically couples together, and (iii) are in direct physical contact with the first and second electrically conductive lines. The first and second electrically conductive lines each comprises a first electrically conductive material. The diffusion barrier region comprises a second electrically conductive material different from the first electrically conductive material. The diffusion barrier region is adapted to prevent a diffusion of the first electrically conductive material through the diffusion barrier region.