Abstract: A method and apparatus for forming an amorphous carbon layer on a substrate is provided. A first portion of the amorphous carbon layer having a high stress level is formed from a hydrocarbon precursor having high dilution ratio, with optional amine precursor included to add stress-elevating nitrogen. A second portion of the amorphous carbon layer having a low stress level is formed on the first portion by reducing the dilution ratio of the hydrocarbon precursor and lowering or eliminating the amine gas. Pressure, temperature, and RF power input may be adjusted instead of, or in addition to, precursor flow rates, and different precursors may be used for different stress levels.

Abstract: A method and apparatus for forming an amorphous carbon layer on a substrate is provided. A first portion of the amorphous carbon layer having a high stress level is formed from a hydrocarbon precursor having high dilution ratio, with optional amine precursor included to add stress-elevating nitrogen. A second portion of the amorphous carbon layer having a low stress level is formed on the first portion by reducing the dilution ratio of the hydrocarbon precursor and lowering or eliminating the amine gas. Pressure, temperature, and RF power input may be adjusted instead of, or in addition to, precursor flow rates, and different precursors may be used for different stress levels.

Abstract: In one embodiment, a method for depositing a material on a substrate is provided which includes positioning a substrate containing a contact within a process chamber, exposing the substrate to at least one pretreatment step and depositing a fill the contact vias by an electroless deposition process. The pretreatment step contains multiple processes for exposing the substrate to a wet-clean solution, a hydrogen fluoride solution, a tungstate solution, a palladium activation solution, an acidic rinse solution, a complexing agent solution or combinations thereof. Generally, the HARC via contains a tungsten oxide surface and the shallow contact via may contain a tungsten silicide surface. In some example, the substrate is pretreated such that both vias are filled at substantially the same time by a nickel-containing material through an electroless deposition process.

Abstract: A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;<˜3.0). Preferably, the cavities are provided with an elemental titanium-free liner to facilitate cavity filling, and the cavities are filled with CVD aluminum that is introduced into the cavities by way of a forcefill at pressures ranging from atmospheric to about 50 MPa, and preferably no more than about 30 MPa, at temperatures ranging from about 100°-300° C. Cavities filled in the foregoing manner exhibit electrical resistance levels that are up to 30% less than structures filled by conventional practices.

Abstract: A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;<˜3.0). Preferably, the cavities are provided with an elemental titanium-free liner to facilitate cavity filling, and the cavities are filled with CVD aluminum that is introduced into the cavities by way of a forcefill at pressures ranging from atmospheric to about 50 MPa, and preferably no more than about 30 MPa, at temperatures ranging from about 100°- 300° C. Cavities filled in the foregoing manner exhibit electrical resistance levels that are up to 30% less than structures filled by conventional practices.

Abstract: A metallization structure, and associated method, for filling contact and via apertures to significantly reduce the occurrence of microvoids and provide desirable grain orientation and texture. A modified barrier structure is set forth for contact apertures, and a modified liner structure is set forth for via apertures. The metallization fill structure for contact apertures includes a first wetting or glue layer of refractory metal on the contact aperture, a layer of TiN on the first wetting layer, a second wetting layer of plasma-treated refractory metal on the barrier layer, a layer of CVD Al on the second wetting refractory metal layer, and a PVD Al alloy to fill the contact aperture. The fill structure for via apertures includes an initial plasma-treated refractory metal liner deposited on the via aperture. A CVD Al liner is positioned on the initial refractory metal liner. A PVD Al alloy layer is positioned on the CVD Al liner to fill the via aperture.

Abstract: A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;<˜3.0). Preferably, the cavities are provided with an elemental titanium-free liner to facilitate cavity filling, and the cavities are filled with CVD aluminum that is introduced into the cavities by way of a forcefill at pressures ranging from atmospheric to about 50 M Pa, and preferably no more than about 30 M Pa, at temperatures ranging from about 100°-300° C. Cavities filled in the foregoing manner exhibit electrical resistance levels that are up to 30% less than structures filled by conventional practices.