Abstract: In optical interconnect systems, information may be encoded in different wavelengths of light in an optical signal in a wavelength division multiplexing (WDM) scheme. The inventors have recognized and appreciated that the data rate of an optical interconnect system may be doubled by employing a polarization multiplexing scheme, where some information is encoded in an optical signal having a first polarization state and other information is encoded in an optical signal having a second, orthogonal polarization state as the different polarizations will act independently while propagating along a fiber. Accordingly, described herein are systems and techniques for optical interconnect systems employing polarization multiplexing.

Abstract: Described herein are systems and techniques for a bidirectional polarization diverse optical transceivers. When an optical signal propagates along a single mode fiber, the single polarization mode gets rotated and may arrive at an optical transceiver with an arbitrary superposition of two orthogonal polarization modes, each of which experience differing optical effects. The bidirectional optical transceivers described herein include one or more features for addressing the differing optical effects so that both polarization modes are received at substantially a same time.

Abstract: Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.

Abstract: Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.

Abstract: Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.

Abstract: Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.

Abstract: Described herein are wavelength division multiplexing (WDM) transceivers configured to support fast, bidirectional communication over optical channels. An optical transceiver comprises a transmitter, a receiver, an input/output (I/O) port and an optical interleaver. The transmitter comprises a first bus waveguide and a plurality of optical modulators coupled to the first bus waveguide, each of the optical modulators being resonant at a respective wavelengths in a first wavelength set. The receiver comprises a second bus waveguide and a plurality of optical filters coupled to the second bus waveguide, each of the optical filters being resonant at a respective wavelength in a second wavelength set. The (I/O) port is coupled to an optical channel.

Abstract: Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.

Abstract: Described herein are wavelength division multiplexing (WDM) transceivers configured to support fast, bidirectional communication over optical channels. An optical transceiver comprises a transmitter, a receiver, an input/output (I/O) port and an optical interleaver. The transmitter comprises a first bus waveguide and a plurality of optical modulators coupled to the first bus waveguide, each of the optical modulators being resonant at a respective wavelengths in a first wavelength set. The receiver comprises a second bus waveguide and a plurality of optical filters coupled to the second bus waveguide, each of the optical filters being resonant at a respective wavelength in a second wavelength set. The (I/O) port is coupled to an optical channel.

Abstract: Described herein are wavelength division multiplexing (WDM) transceivers configured to support fast, bidirectional communication over optical channels. An optical transceiver comprises a transmitter, a receiver, an input/output (I/O) port and an optical interleaver. The transmitter comprises a first bus waveguide and a plurality of optical modulators coupled to the first bus waveguide, each of the optical modulators being resonant at a respective wavelengths in a first wavelength set. The receiver comprises a second bus waveguide and a plurality of optical filters coupled to the second bus waveguide, each of the optical filters being resonant at a respective wavelength in a second wavelength set. The (I/O) port is coupled to an optical channel.

Abstract: Described herein are compact, power efficient photonic processors deigned to handle general matrix-matrix (GEMM) operations. A photonic processor may comprise a controller, an optical interferometer, a plurality of signal drivers, and an optical receiver. The controller is configured to obtain a vector of input values and a matrix of parameters. The optical interferometer comprises an output and a plurality of optical phase shifters. Each signal driver of the plurality of signal drivers is configured to control a respective phase shifter to phase shift light traveling in the optical interferometer based on i) a polarity set by a respective parameter of the matrix, and ii) an amount set by a respective input value of the vector. The optical receiver is coupled to the output of the optical interferometer.

Abstract: Described herein is a packaging approach that employs a remapping layer to maintain compatibility to different types of electronic chips while allowing chip designers to standardize the layout of the electrical interface of a photonic interposer. A remapping layer remaps the electrical interface of an electronic chip to the electrical interface of a photonic interposer. Remapping layers may be implemented in various ways, including for example as monolithic electronic interposers and/or as individual remapping chips. In some embodiments, to reduce manufacturing costs, remapping layers may be implemented using passive electronics (without transistors). Because remapping layers are significantly less costly to manufacture than photonic interposers, shifting the need to provide ad hoc electrical interfaces from the photonic interposer to the remapping layer enhances the applicability of photonic interposers in computational, telecom and datacom settings.

Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix multiplications (e.g., matrix vector multiplications). Matrix multiplications are broken down in scalar multiplications and scalar additions. Some embodiments relate to devices for performing scalar additions in the optical domain. One optical adder, for example, includes an interferometer having a plurality of phase shifters and a coherent detector. Leveraging the high-speed characteristics of these optical adders, some processors are sufficiently fast to support clocks in the tens of gigahertz of frequency, which represent a significant improvement over conventional electronic processors.

Abstract: Techniques for efficiently tuning of optical resonant devices (e.g., micro-ring modulators (MRM) or add/drop filters) are described. The techniques described herein can be used in photonic communication systems that transmit data using several wavelengths of light sharing a common optical waveguide or a common fiber, e.g., wavelength division multiplexing (WDM) systems. These techniques may involve varying the way in which resonant wavelengths are mapped to the wavelengths of emission until it is determined that the power consumption is appropriate (e.g., below a certain threshold value). This significantly reduces the amount of power needed to ensure proper alignment between wavelength of emission and resonant wavelengths.

Abstract: Described herein are techniques for intra-chip communication within tiled photonic interposers. A photonic interposer may rely on a combination of photonic lanes and electric lanes. For example, a photonic interposer may comprise a photonic integrated circuit (PIC) lithographically patterned with an array of photonic tiles, each photonic tile comprising an on-chip communication unit. The array of photonic tiles is arranged in rows and columns. A plurality of electric lanes place the on-chip communication units of photonic tiles of different rows in electrical communication with one another. A plurality of photonic lanes place the on-chip communication units of photonic tiles of different columns in optical communication with one another.

Abstract: Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.

Abstract: Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.

Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix multiplications (e.g., matrix vector multiplications). Matrix multiplications are broken down in scalar multiplications and scalar additions. Some embodiments relate to devices for performing scalar additions in the optical domain. One optical adder, for example, includes an interferometer having a plurality of phase shifters and a coherent detector. Leveraging the high-speed characteristics of these optical adders, some processors are sufficiently fast to support clocks in the tens of gigahertz of frequency, which represent a significant improvement over conventional electronic processors.

Abstract: A light steeling system and method for diffractive steering of electromagnetic radiation such as visible light is disclosed. Embodiments of the light steering system include leaky-mode SAW modulators as light modulator devices. The SAW modulators preferably include reflective diffractive gratings. The gratings are mounted to/patterned upon an exit face that opposes an exit surface of the SAW modulator, in one example. Steering of light signals emitted from the SAW modulators in these systems can be accomplished by varying wavelength of light signals introduced to the SAW modulators, and/or by varying frequency of RF drive signals applied to the SAW modulators. In addition, light field generators that incorporate SAW modulators of the proposed light steering system within displays of the light field generators are also disclosed.

Abstract: A micro-coaxial wire has an overall diameter in a range of 0.1 ?m-550 ?m, a conductive core of the wire has a cross-sectional diameter in a range of 0.05 ?m-304 ?m, an insulator is disposed on the conductive core with thickness in a range of 0.005 ?m-180 ?m, and a conductive shield layer is disposed on the insulator with thickness in a range of 0.009 ?m-99 ?m.