Abstract: “A compensating circuit for use in a switch circuit comprising scaled current steering switches, a switch circuit comprising the compensating circuit, and a method for minimising time-skew in switching scaled current steering switches” An eight bit current steering DAC comprising scaled current steering switches (ST0,SF0,ST(n−1),SF(n−1)) (where n=8) comprises a comprising plurality of compensating MOS switches (SCT0 and SCF0 to SCT(n−1) for minimising time-skew when switching selected ones of the current steering switches from one state to another. The compensating switches (SCT,SCF) are of type similar to the current steering switches (STi and SFi), and are sized so that the combined switching load presented to the corresponding driver circuit (Di) by the sum of the parasitic load capacitance of the current steering switch (STi or SFi) and the corresponding compensating switch (SCTi or SCFi) is substantially similar for each driver circuit (Di).

Abstract: An eight bit current steering DAC comprising scaled current steering switches (ST0,SF0,ST(n−1),SF(n−1)) (where n=8) comprises a scaled load compensating circuit (12) comprising a plurality of compensating MOS switches (SCT0 and SCF0 to SCT(n−1) to SCF(n−1)). The compensating switches (SCT,SCF) are of type similar to the current steering switches (ST1 and SFi), and are sized so that the combined switching load presented to the corresponding driver circuit D1 by the sum of the parasitic load capacitance of the current steering switches (ST1 or SF1) and the corresponding parasitic switching load capacitance of the corresponding compensating switch (SCTi or SCF1) is substantially similar for each driver circuit D1. Additionally, by virtue of the fact that the switching load capacitance, and in turn the switching loads presented to the driver circuits (D1) are similar, the driver circuits (D1) are therefore also similar to each other.