Abstract: A starter circuit for a fluorescent tube lamp is connected between the cathode heaters of the tube to provide an initial heating current and then changes to a high impedance to ignite the tube. The circuit is fed by raw rectified a.c. and has a main thyristor requiring a high holding current to maintain the initial conduction. The current through the main thyristor sets up a voltage across a series diode which triggers a second thyristor to reduce the gate voltage of the main thyristor. The main thyristor ceases conduction when the current falls below the holding value and the inductive ballast impedance then produces a high energy striking pulse for the tube. The pulse voltage is limited to increase its duration. One embodiment generates a single pulse only each time the circuit is switched on and another embodiment produces pulses for a period of time before becoming quiescent. The main thyristor and the voltage limiting means are embodied in a monolithic semiconductor structure.

Abstract: A starter circuit for a fluorescent tube lamp is connected between the cathode heaters of the tube to provide an initial heating current and then changes to a high impedance to ignite the tube. The circuit is fed by raw rectified a.c. and has a main thyristor requiring a high holding current to maintain the initial conduction. The current through the main thyristor sets up a voltage across a series diode which triggers a second thyristor to reduce the gate voltage of the main thyristor. The main thyristor ceases conduction when the current falls below the holding value and the inductive ballast impedance then produces a high energy striking pulse for the tube. The pulse voltage is limited to increase its duration. One embodiment generates a single pulse only each time the circuit is switched on and another embodiment produces pulses for a period of time before becoming quiescent. The main thyristor and the voltage limiting means are embodied in a monolithic semiconductor structure.

Abstract: A semiconductor switch device suitable for a.c. power control includes three 4-layer switch components in parallel in a single body of semiconductor material. First and second components are of the same polarity and of opposite polarity to the third component. One end connection of the second component is taken out as a secondary gate connection separate from the corresponding connections of the first and third components. In a preferred mode of use, the secondary gate connection is maintained at a d.c. potential relative to the corresponding connections of the first and third components so as to enable the second component to be conducting during the zero crossings of the a.c. supply and able to maintain the internal voltages required for conduction of either or both of the other components.

Abstract: A completely integrated npn Darlington stage is provided using an n-type film deposited on an n+ substrate. A p-type boron base is first partially diffused into the n layer, then an oxide window is cut into the oxide formed during the base diffusion, in the area designated for the speedup transistor. A high temperature boron deposition is performed in the oxide window, and the base diffusion completed. The times of the base diffusion steps are chosen so that the penetration of the more lightly doped region slightly exceeds that of the heavily doped region. Oxide windows are then cut for the driver, output and speedup device emitters and the emitter diffusion performed in standard manner. Fabrication is completed using normal single diffused techniques. The effect of the heavy doping of the base region of the speedup transistor is to create a very low gain transistor which has a BV.sub.CEO nearly equal to the BV.sub.CEX rating.

Abstract: A completely integrated npn Darlington stage is provided using an n-type film deposited on an n+ substrate. A p-type boron base is first partially diffused into the n layer, then an oxide window is cut into the oxide formed during the base diffusion, in the area designated for the speedup transistor. A high temperature boron deposition is performed in the oxide window, and the base diffusion completed. The times of the base diffusion steps are chosen so that the penetration of the more lightly doped region slightly exceeds that of the heavily doped region. Oxide windows are then cut for the driver, output and speedup device emitters and the emitter diffusion performed in standard manner. Fabrication is completed using normal single diffused techniques. The effect of the heavy doping of the base region of the speedup transistor is to create a very low gain transistor which has a BV.sub.CEO nearly equal to the BV.sub.CEX rating.