Patents by Inventor Anthony Lell
Anthony Lell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240077925Abstract: Circuits, systems and methods are provided. A circuit includes a subsystem, an interface, and a debugger. The interface includes power processing and management (PPM) circuitry coupled to the subsystem, and arbitration logic coupled to the PPM circuitry. In operation, the debugger issues a debug request to the arbitration logic to perform a debug operation on the subsystem, and, in response to the debug request, the arbitration logic provides an interrupt associated with the subsystem to the PPM circuitry. The PPM circuitry, in response to the interrupt and a determination that the subsystem is OFF, powers on the subsystem and provides a notification to the arbitration logic indicating that the subsystem is ON. The PPM circuitry also receives a notification from the arbitration logic that the debug operation related to the debug request is complete, and powers off the subsystem in response to that notification.Type: ApplicationFiled: November 8, 2023Publication date: March 7, 2024Inventors: Jose Luis FLORES, Gary Augustine COOPER, Amritpal Singh MUNDRA, Anthony LELL, Jason Lynn PECK
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Publication number: 20230418718Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.Type: ApplicationFiled: September 7, 2023Publication date: December 28, 2023Inventors: NIRAJ NANDAN, HETUL SANGHVI, MIHIR MODY, GARY COOPER, ANTHONY LELL
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Patent number: 11847006Abstract: An integrated circuit includes: a debugger; and an interface coupled to the debugger. The interface has: arbitration logic coupled to the debugger; a power processor coupled to the arbitration logic; and a power management network coupled to the power processor. The integrated circuit also includes subsystems coupled to the interface. The debugger is configured to perform debugging operations of the subsystems via the interface.Type: GrantFiled: December 31, 2020Date of Patent: December 19, 2023Assignee: Texas Instruments IncorporatedInventors: Jose Luis Flores, Gary Augustine Cooper, Amritpal Singh Mundra, Anthony Lell, Jason Lynn Peck
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Patent number: 11789836Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.Type: GrantFiled: August 31, 2021Date of Patent: October 17, 2023Assignee: Texas Instruments IncorporatedInventors: Niraj Nandan, Hetul Sanghvi, Mihir Mody, Gary Cooper, Anthony Lell
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Publication number: 20220114120Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.Type: ApplicationFiled: December 21, 2021Publication date: April 14, 2022Inventors: Mihir MODY, Niraj NANDAN, Hetul SANGHVI, Brian CHAE, Rajasekhar Reddy ALLU, Jason A.T. JONES, Anthony LELL, Anish REGHUNATH
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Patent number: 11276134Abstract: A reconfigurable image processing pipeline includes an image signal processor (ISP), a control processor, and a local memory. ISP processes raw pixel data for a frame based on an image processing parameter and provides lines of processed pixel data to control processor via a first interface. For each region of interest (ROI) in the frame, ISP generates auto-exposure and auto-white balance (2A) statistics based on the lines for the ROI and writes them to the local memory via a second interface. Control processor reads 2A statistics from the local memory, determines the image processing parameter based on them, and provides the image processing parameter to ISP. ISP also generates an integer N bin histogram for control processor, which sums a portion of the N total bins and compares the summed bin count to a lighting transition threshold. The image processing parameter is further based on the comparison.Type: GrantFiled: April 14, 2020Date of Patent: March 15, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mihir Narendra Mody, Niraj Nandan, Rajat Sagar, Shashank Dabral, Anthony Lell, Brijesh Jadav
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Patent number: 11237991Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.Type: GrantFiled: August 17, 2020Date of Patent: February 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mihir Mody, Niraj Nandan, Hetul Sanghvi, Brian Chae, Rajasekhar Reddy Allu, Jason A. T. Jones, Anthony Lell, Anish Reghunath
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Publication number: 20210397528Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.Type: ApplicationFiled: August 31, 2021Publication date: December 23, 2021Inventors: NIRAJ NANDAN, HETUL SANGHVI, MIHIR MODY, GARY COOPER, ANTHONY LELL
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Patent number: 11144417Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.Type: GrantFiled: December 31, 2018Date of Patent: October 12, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Niraj Nandan, Hetul Sanghvi, Mihir Mody, Gary Cooper, Anthony Lell
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Publication number: 20210208657Abstract: An integrated circuit includes: a debugger; and an interface coupled to the debugger. The interface has: arbitration logic coupled to the debugger; a power processor coupled to the arbitration logic; and a power management network coupled to the power processor. The integrated circuit also includes subsystems coupled to the interface. The debugger is configured to perform debugging operations of the subsystems via the interface.Type: ApplicationFiled: December 31, 2020Publication date: July 8, 2021Inventors: Jose Luis FLORES, Gary Augustine COOPER, Amritpal Singh MUNDRA, Anthony LELL, Jason Lynn PECK
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Publication number: 20210209719Abstract: A reconfigurable image processing pipeline includes an image signal processor (ISP), a control processor, and a local memory. ISP processes raw pixel data for a frame based on an image processing parameter and provides lines of processed pixel data to control processor via a first interface. For each region of interest (ROI) in the frame, ISP generates auto-exposure and auto-white balance (2A) statistics based on the lines for the ROI and writes them to the local memory via a second interface. Control processor reads 2A statistics from the local memory, determines the image processing parameter based on them, and provides the image processing parameter to ISP. ISP also generates an integer N bin histogram for control processor, which sums a portion of the N total bins and compares the summed bin count to a lighting transition threshold. The image processing parameter is further based on the comparison.Type: ApplicationFiled: April 14, 2020Publication date: July 8, 2021Inventors: Mihir Narendra MODY, Niraj NANDAN, Rajat SAGAR, Shashank DABRAL, Anthony LELL, Brijesh JADAV
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Publication number: 20200379928Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.Type: ApplicationFiled: August 17, 2020Publication date: December 3, 2020Inventors: Mihir MODY, Niraj NANDAN, Hetul SANGHVI, Brian CHAE, Rajasekhar Reddy ALLU, Jason A.T. JONES, Anthony LELL, Anish REGHUNATH
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Patent number: 10747692Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.Type: GrantFiled: December 27, 2018Date of Patent: August 18, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mihir Mody, Niraj Nandan, Hetul Sanghvi, Brian Chae, Rajasekhar Reddy Allu, Jason A. T. Jones, Anthony Lell, Anish Reghunath
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Publication number: 20200210301Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.Type: ApplicationFiled: December 31, 2018Publication date: July 2, 2020Inventors: NIRAJ NANDAN, Hetul Sanghvi, Mihir Mody, Gary Cooper, Anthony Lell
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Publication number: 20200210351Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.Type: ApplicationFiled: December 27, 2018Publication date: July 2, 2020Inventors: Mihir MODY, Niraj NANDAN, Hetul SANGHVI, Brian CHAE, Rajasekhar Reddy ALLU, Jason A.T. JONES, Anthony LELL, Anish REGHUNATH
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Patent number: 9871965Abstract: A signal processing chain implements wide dynamic range (WDR) multi-frame processing including receiving raw image signals from a WDR sensor including a plurality of frames including a first frame including first exposure time pixel data and a second frame including second exposure time pixel data. Statistics for camera control are generated including first statistics for the first pixel data and second statistics for the second pixel data. The first and second pixel data are merged using WDR merge algorithm in a WDR merge block which utilizes the first and second statistics to generate a raw higher bit width single frame image. The single frame image is post-processed in post-processing block using at least a defect pixel correction algorithm, and at least a portion of tone mapping is performed on the single frame image after the post-processing to provide an output toned mapped image.Type: GrantFiled: June 15, 2016Date of Patent: January 16, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shashank Dabral, Mihir Narendra Mody, Gang Hua, Anthony Lell, Niraj Nandan, Rajashekhar Allu
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Publication number: 20170223267Abstract: A signal processing chain implements wide dynamic range (WDR) multi-frame processing including receiving raw image signals from a WDR sensor including a plurality of frames including a first frame including first exposure time pixel data and a second frame including second exposure time pixel data. Statistics for camera control are generated including first statistics for the first pixel data and second statistics for the second pixel data. The first and second pixel data are merged using WDR merge algorithm in a WDR merge block which utilizes the first and second statistics to generate a raw higher bit width single frame image. The single frame image is post-processed in post-processing block using at least a defect pixel correction algorithm, and at least a portion of tone mapping is performed on the single frame image after the post-processing to provide an output toned mapped image.Type: ApplicationFiled: June 15, 2016Publication date: August 3, 2017Inventors: SHASHANK DABRAL, MIHIR NARENDRA MODY, GANG HUA, ANTHONY LELL, NIRAJ NANDAN
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Patent number: 8598932Abstract: A clock divider is provided that is configured to divide a high speed input clock signal by an odd, even or fractional divide ratio. The input clock may have a clock cycle frequency of 1 GHz or higher, for example. The input clock signal is divided to produce an output clock signal by first receiving a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates the divide ratio is N.5 when the fractional indicator is one and indicates the divide ratio is N when the fractional indicator is zero. F is set to 2(N.5)/2 for a fractional divide ratio and F is set to N/2 for an integer divide ratio. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd.Type: GrantFiled: May 6, 2013Date of Patent: December 3, 2013Assignee: Texas Instruments IncorporatedInventors: Ramakrishnan Venkatasubramanian, Anthony Lell, Raguram Damodaran
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Publication number: 20130243148Abstract: A clock divider is provided that is configured to divide a high speed input clock signal by an odd, even or fractional divide ratio. The input clock may have a clock cycle frequency of 1 GHz or higher, for example. The input clock signal is divided to produce an output clock signal by first receiving a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates the divide ratio is N.5 when the fractional indicator is one and indicates the divide ratio is N when the fractional indicator is zero. F is set to 2(N.5)/2 for a fractional divide ratio and F is set to N/2 for an integer divide ratio. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd.Type: ApplicationFiled: May 6, 2013Publication date: September 19, 2013Inventors: Ramakrishnan Venkatasubramanian, Anthony Lell, Raguram Damodaran
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Patent number: 8532247Abstract: A clock divider divides a high speed input clock signal by an odd, even or fractional divide ratio. The clock divider receives a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates a fractional divide ratio when one and an integral divide ratio when zero. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. The clock divider synthesizes one period of an output clock signal in response to each assertion of the count indicator for a fractional divide ratio and synthesizes one period of the output clock signal in response to two assertions of the count indicator for an integral divide ratio.Type: GrantFiled: September 28, 2011Date of Patent: September 10, 2013Assignee: Texas Instruments IncorporatedInventors: Ramakrishnan Venkatasubramanian, Anthony Lell, Raguram Damodaran