Abstract: Techniques for controlling bandwidth in a core are described. An exemplary core includes a memory bandwidth monitor per thread local to the core, each thread's local bandwidth monitor to at least allocate bandwidth for memory requests originating from the thread according to a class of service level stored in a field of quality of service (QOS) model-specific register (MSR), the class of service level pointed to by a class of service field in a platform quality of service MSR; and execution resources to support execution of at least one thread of the core.

Abstract: In one embodiment, an apparatus comprises: a first circuit to compact a plurality of data blocks to a compacted data block and to compact a plurality of error correction codes (ECCs) associated with the plurality of data blocks to a compacted ECC; and a second circuit to generate a generated ECC for the compacted data block. The apparatus may directly send the plurality of data blocks to a destination circuit without error detection on the plurality of data blocks based at least in part on the compacted ECC and the generated ECC. Other embodiments are described and claimed.

Abstract: Techniques for quality of service (QoS) support for input/output devices and other agents are described. In embodiments, a processing device includes execution circuitry to execute a plurality of software threads; hardware to control monitoring or allocating, among the plurality of software threads, one or more shared resources; and configuration storage to enable the monitoring or allocating of the one or more shared resources among the plurality of software threads and one or more channels through which one or more devices are to be connected to the one or more shared resources.

Abstract: In one embodiment, an apparatus comprises: a first circuit to compact a plurality of data blocks to a compacted data block and to compact a plurality of error correction codes (ECCs) associated with the plurality of data blocks to a compacted ECC; and a second circuit to generate a generated ECC for the compacted data block. The apparatus may directly send the plurality of data blocks to a destination circuit without error detection on the plurality of data blocks based at least in part on the compacted ECC and the generated ECC. Other embodiments are described and claimed.

Abstract: An embodiment of an integrated circuit may comprise first circuitry to manage a memory in accordance with a page size and a channel interleave granularity, and second circuitry coupled to the first circuitry, the second circuitry to store data in a primary region of the memory at a primary address, and manage a mirror of the data in a secondary region of the memory at a secondary address at a regional granularity on demand at run time. Other embodiments are disclosed and claimed.

Abstract: Apparatus, method, and system for efficiently identifying and tracking cold memory pages are disclosed. The apparatus in one embodiment includes one or more processor cores to access memory pages stored in the memory by issuing access requests to the memory and a page index bitmap to track accesses made by the one or more processor cores to the memory pages. The tracked accesses are usable to identify infrequently-accessed memory pages, where the infrequently-accessed memory pages are removed from the memory and stored in a secondary storage.

Abstract: An apparatus is described. The apparatus includes a processor. The processor includes a memory controller to read and write from a memory. The memory controller includes error correction coding (ECC) circuitry to correct errors in data read from the memory. The processor includes register space to track read data error information. The processor includes an embedded controller. The processor includes local memory coupled to the embedded controller. The embedded controller is to read the read data error information and store the read data error information in the local memory.

Abstract: An apparatus for efficiently identifying and tracking cold memory pages. The apparatus includes a memory to store memory pages, one or more processor cores to access the memory pages stored in the memory by issuing access requests to the memory; and a page index bitmap to track accesses made by the one or more processor cores to the memory pages stored in the memory. The tracked accesses are usable to identify infrequently-accessed memory pages, wherein the infrequently-accessed memory pages are removed from the memory and stored in a secondary storage.