Abstract: Programming of the input and output paper handling setup of a high speed reprographic system can adversely affect the throughput of the system. A method or system includes a control system that examines the proposed setup and then determine if any of these options results in a loss of throughput. If such losses are detected and exceed a predetermined threshold, the operator of the device will be informed and given the opportunity to change the setup to reduce the throughput loss.

Abstract: A digital printer for printing images in response to full-frame, two-dimensional digital image data input from an outside source. The digital printer is a novel combination of a two dimensional backlight for producing full frame illumination in a single flash, a photoreceptor sensitive to light emanating from the backlight, a two-dimensional, transmissive light valve, an imaging system, and a driver. The light valve is disposed between the backlight and the photoreceptor so that light from the backlight is transmitted through the light valve, producing a full-frame, two dimensional image on the photoreceptor in response to a single flash of the backlight. The full-frame, two dimensional image corresponds to a pattern formed on the light valve in response to the full-frame, two dimensional digital image data. The imaging system is disposed between the light valve and the photoreceptor, such that it focuses the full-frame, two dimensional image onto the photoreceptor.

Abstract: An electronic image processing apparatus comprising an electronic scanner and an electronic printer for forming an image, a controller for directing the operation of the image processing means, the controller including a mass memory device for storing data to be printed, random access memory, a printer control, and a Resource Manager for ensuring access to the random access memory for conveying data from the mass memory device to the printer via the random access memory, the Resource Manager including a mass memory device scheduler to provide printer access to the random access memory, the mass memory device scheduler having a reservation queue to reserve mass memory device access at predetermined times, delay means to determine that access to the mass memory device is invalid within a given time, and means to convey disk request operations to said reservation queue in order to provide guaranteed random access mernory at predetermined times.

Abstract: In accordance with the present invention there is provided a method for scheduling transfers in a printing machine of the type having a scheduler communicating with both a first disk and a second disk, the first and second disks having a combined bandwidth. The method for scheduling comprises the following steps: First, a first transfer to be performed on a first location of the first disk during a first time interval and a second transfer to be performed on a second location of the first disk during a second time interval are both scheduled, with the scheduler, so that a first time gap interval exists between the first time interval and the second time interval.

Abstract: A layered document services architecture facilitating operation and interconnection of electronic printing systems with both resident and non-resident work inputs.

Abstract: An electronic printing system with plural hard disks for storing system files in which file management information is held in a Volume Allocation Table in internal system RAM memory with file management updates queued in NVM, with the contents of the Volume Allocation Table transferred to external disk memory when the queue of file management updates in NVM reaches a predetermined size.

Abstract: An electronic image processing apparatus having image processing resources including a controller for directing the operation of the image processing resources, the controller including a disk memory, the method of controlling mass memory device bandwidth access during an access time window including guaranteeing access to the memory for predetermined time periods for a first set of image processing resources during each access time window, a second set of image processing resources having access subordinate to the first set of image processing resources, maintaining a record of mass memory device access for the first set of image processing resources during each access time window, receiving a memory access request from the first set of image processing resources, determining that said resource utilization does not exceed the predetermined time period, and allowing current access to the mass memory device by the image processing resource.

Abstract: A method and apparatus provide for recovering from faults in an electronic reprographic system for scanning and synchronously or asynchronously processing and printing a plurality of jobs. The system is monitored for the occurrence of faults in a job, the faults are identified and recorded through a fault logging service and a specific response is initiated to the faults recorded by the fault logging service. Provision is made for using the log offline to determine the cause and effect of problems created by the faults in the system. The invention further provides for using the log online to monitor the occurrence of hardware faults in the system, and initiate the appropriate online diagnostic routine, whose response can further isolate a suspected problem.

Abstract: A state controller for an electronic reprographic system for controlling system operations when processing requests in which the system has a plurality of hardware and software system components providing discrete services for processing requests and maintaining operation of the system, and job programming means including a display screen for inputting requests, including: a state holder for monitoring the current operating state of the system components; plural discrete job processing virtual machines with each of the virtual machines having at least one service associated with it for implementing the virtual machine; each of the services having at least one of the system components for carrying out the service; and a scheduler for managing resources of and setting priorities for the virtual machines to process the requests in an efficient manner, the scheduler being adapted to cause memory from a first one of the virtual machines to be distributed to a second one of the virtual machines when the second one

Abstract: The present invention is to designate one of the processors in a multiprocessor control as the master processor. All the other processors report their faults to the master processor. When it receives a fault message, the master processor records the type of fault and the source of the message in suitable memory locations. The master will also time stamp the fault message to identify the first fault message. Finally, the master will transmit a message to itself to verify that the master's communication channel is valid to verify whether the master processor itself or one of the remote processors is faulty.

Abstract: The present invention is a pair of counters associated with the control elements in a complex control system, in particular, counters associated with the intelligent processors in a multiprocessor control. Preferably, the counters are maintained in nonvolatile memory and one of the counters for each remote records software crashes experienced in both standby and run mode. The other counter records total software crashes during normal machine operation. These counters provide information on the location and type of software crashes.In another aspect of the invention, a procedure is provided for the Tech Rep to force the machine into a software crash. The Tech Rep can then interrogate the content of RAM locations before the RAM locations are initialized by the machine reset. The contents of various RAM locations can be selectively displayed for diagnosis.

Abstract: A multiprocessor control for a machine including a first executing portion communicating with a first processor and a second executing portion communicating with a second processor. The processors execute a plurality of tasks with each of said tasks residing in one or the other of the processors. Each of the tasks is executed in one or the other of the processors and each of the tasks comprises a block of instructions. A plurality of tasks are operated on by providing a start instruction for the execution of tasks, identifying a first task to be started by said start instruction, initiating the execution of the first task by the start instruction, identifying a second task to be started by the start instruction, and initiating the execution of the second task by the start instruction before the execution of the first task is complete.

Abstract: The present invention is a multiprocessor machine control having at least one processor for performing input and output operations and communicating with a master processor over a communication channel. Common synchronizing signals are conveyed to both the input/output processor and the master processor independent of the communication channel. This provides the input/output processor with immediate access to timing and synchronizing information for prompt response to general control information from the master processor. The master processor downloads instructions or provides general instructions to the input/output processor. These downloaded instructions are given priority and timely executed without further communication with the master processor. At completion of the operation the master processor is informed that the particular operation has been performed.

Abstract: An Interrupt Manager for servicing interrupts. An interrupt is performed only after an atomic operation (Operating System instruction) is completed. After completion of each operating system instruction, a first command immediately allows any interrupt to be serviced. A second command then immediately closes out any interrupts, allowing for the execution of the next operating system instruction.

Abstract: The present invention is a multiprocessor machine control system in which the failure of one of the processors to reset can be ignored by the rest of the control system. In particular, a software crash or other abnormality on one of the processors will generate a reset procedure. If the processor cannot be reset, this will indicate a processor board failure such as a hardware failure. If the processor and its controlled elements are not crucial to the machine operation, then the control wll ignore the failed processor as though it were not in the control system, and continue with machine operation.

Abstract: A control system is provided to automatically alter the control of a machine to respond to a different number of pitches or images that the machine can manage at one time. A flag in memory is monitored and in response to the flag, the machine control is adjusted to manage a different number of pitches during the operation of the machine and to provide clock signals for the timed actuation of events in each of the pitches.

Abstract: The present invention includes a plurality of input/output processors communicating with a master processor. Each of the input/output processors has a filtering mechanism to filter the inputs before transmission to the master over the communication channel precluding the necessity of filtering at the master. More importantly, the shared communications system is not loaded down with every change of an input. Because of this feature, only meaningful changes are put on the communication line, thus substantially reducing its load which makes its effective response time stay high. The inputs when received at the master can be immediately handled to improve the central processor response time. Two types of filtering are provided, in particular, transition and debounce filtering to respond to switch and sensor inputs. Also, there is provided a means to programmably select the type of filter and the time period of filtering.

Abstract: The present invention is a means to race two or more conditions against each other to trigger a unique control response. In particular, a portion of a machine control is suspended upon the occurrence of conditions such as an input, a time delay, availability of data, or completion of a task. These conditions race against one another. That is, the occurrence of one of the conditions will initiate the response, and all other conditions will then be ignored. The type of response depends upon the particular condition that occurred first.

Abstract: The present invention is monitoring the control, in particular, software crashes in a multiprocessor machine control system to prevent machine malfunctions. Benchmarks or key operations tracked include, for example, monitoring that the number of tasks to be completed by the control is not beyond the capacity of the control to respond. These recorded benchmarks enable one or both of two paths of progressively more complex analysis. In particular, there is a diagnostic path that leads first to the isolation of a particular control element in a multi-element control that contains a fault and then to a more comprehensive recording of the fault history for each individual control element. There is also a path for maintaining machine operation. In this path, a first level of response is to merely reset the various control elements.

Abstract: The present invention is an electronic controller that is partially a virtual machine. The virtual machine portion of the controller comprises an Operating System including two major levels--namely, an Instruction Module level and a Primitive level. Directives corresponding to macros in a physical machine (microprocessor) architecture are the top level of the control. The Directives shield the Operating System structure from changes in the compiler, allow for changes in the Operating System internal structure and abstract out from the compiler unnecessary operating system details. Instruction Modules and Primitives make up the Operating System. Instruction Modules are the middle level and correspond to assembly language instructions in a physical machine. They are the smallest executable, nonpreemptive unit in the virtual machine.