Abstract: A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number.

Abstract: A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number.

Abstract: An apparatus and method are provided for removing gases produced during off-service cleaning of a processing chamber which operates under vacuum in a wafer fabrication tool. The apparatus includes a ventilation fixture providing a manifold having an internal cavity in fluid communication with a source of vacuum and at least one intake aperture, and a quick disconnect fitting connected to the source of vacuum and in fluid communication with the internal cavity. The manifold is portable and located adjacent to the processing chamber during cleaning.

Abstract: A high speed analog-to-digital converter employs a comparator having first and second units cross coupled in a positive feedback loop. The units are alternately connected to an input voltage and a reference voltage, after which positive feedback is introduced established, and a differential output established. The arrangement is fully symmetric, and balanced and rejects common-mode switching noise.

Abstract: The invention discloses a method and an apparatus for implementing an L phase clock in conjuction with L counters, where L is an integer, to count at a frequency scalable by L.

Abstract: An IDCT, or Inverse Discrete Cosine Transform, method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by .sqroot.2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of .sqroot.2.

Abstract: An IDCT, or Inverse Discrete Cosine Transform, method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by .sqroot.2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of .sqroot.2.

Abstract: An IDCT method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by .sqroot. 2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of .sqroot. 2.

Abstract: The invention discloses a method and an apparatus for implementing an L phase clock in conjuction with L counters, where L is an integer, to count at a frequency scalable by L.

Abstract: An IDCT, or Inverse Discrete Cosine Transform, method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by .sqroot.2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of .sqroot.2.

Abstract: A programmable logic output driver includes a bias generator (100), a current mirror (200) and an output stage (300), there being a digital programming feature to maintain the output voltage slew rate at an acceptable value for either high or low values of load capacitances. The driver is programmable and can maintain a constant value of driver output resistance in the circumstances where the load voltage approaches the full swing logic voltage. In the preferred embodiment, the programmed output resistance is independent of variations in process, temperature and VDD supply voltage. TTL loads are driven with the minimum amount of required output current. Because of the constant resistance, the driver supplies a specified amount of current to the load even when the load is pulled down to a specified voltage.

Abstract: A method of mass spectrometry and a mass spectrometer for the analysis of a sample, the mass spectrometer comprising means for producing ions from the sample and a magnetic sector for analyzing the ions, wherein the magnetic field of the magnetic sector is generated by passage of a magnet current controlled by a digital control signal representative of a sequence of integers generated by a computer. According to the invention, means are provided for generating the magnet current in exponential relation to the sequence of integers. In contrast to prior spectrometers, the invention provides peak switching and mass selection across the mass range with a constant number of integer steps per mass peak, thereby facilitating the digital selection of any particular mass peak, particularly those at low mass.

Abstract: A collapsible mop pad holder comprises two opposite end leaves pivotally mounted on a central support which is connectible to a handle, and a catch operative to latch the end leaves in an erected condition. The catch comprises a latch member pivotally mounted on one of the leaves and depressible from a latching position, in which it engages the other leaf to latch both leaves together and thus maintains the erected condition of the holder, to an unlatching position in which it is retained until the mop pad holder is collapsed. The arrangement is such that on re-erection of the mop pad holder the latch member automatically re-assumes the latching position.