Patents by Inventor Anthony M. Palagonia
Anthony M. Palagonia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6574925Abstract: An emergency stairwell for a building having multiple floors comprising: at least one landing associated with each the floor, each landing increasing in width in at least one horizontal direction from an uppermost landing of an upper floor to a lowermost landing of a lower floor; and at least one set of stairs extending between adjacent pairs of landings.Type: GrantFiled: January 29, 2002Date of Patent: June 10, 2003Assignee: Maximus TechnologiesInventors: Anthony M. Palagonia, Stuart K. J. Smyth
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Publication number: 20030074848Abstract: An emergency stairwell for a building having multiple floors comprising: at least one landing associated with each the floor, each landing increasing in width in at least one horizontal direction from an uppermost landing of an upper floor to a lowermost landing of a lower floor; and at least one set of stairs extending between adjacent pairs of landings.Type: ApplicationFiled: January 29, 2002Publication date: April 24, 2003Inventors: Anthony M. Palagonia, Stuart K.J. Smyth
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Patent number: 6425092Abstract: Redundant chip sections held in standby are substituted for chip sections that are at risk of over heating based on certain sensor signals. When these signals are received operations of the chip section at risk IS transferred to a redundant chip section and the chip section at risk is shut down. After the original chip section has cooled, it becomes available as a replacement chip section itself. The sensor signals may be based on temperature values, elapsed operation time, and number or rate of operations within a chip section.Type: GrantFiled: June 17, 1998Date of Patent: July 23, 2002Assignee: International Business Machines CorporationInventors: Richard J. Evans, Scott W. Gould, Anthony M. Palagonia, Sebastian T. Ventrone
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Patent number: 6400166Abstract: A monolithic probe having an integral fine probe point, pressure spring, conductive line, and connector for contacting semiconductor devices to be tested and a method of construction of said probe is described. Integration of a serpentine spring into the probe body reduces breakage and improves contact reliability. Standard, coaxial, triaxial, and Kelvin probes are described. The methods of construction described utilize standard semiconductor processes. The probes may be fabricated to very small dimensions.Type: GrantFiled: April 15, 1999Date of Patent: June 4, 2002Assignee: International Business Machines CorporationInventors: Gordon M. Babson, Anthony M. Palagonia
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Publication number: 20020005728Abstract: A monolithic probe having an integral fine probe point, pressure spring, conductive line, and connector for contacting semiconductor devices to be tested and a method of construction of said probe is described. Integration of a serpentine spring into the probe body reduces breakage and improves contact reliability. Standard, coaxial, triaxial, and Kelvin probes are described. The methods of construction described utilize standard semiconductor processes. The probes may be fabricated to very small dimensions.Type: ApplicationFiled: April 15, 1999Publication date: January 17, 2002Inventors: GORDON M. BABSON, ANTHONY M. PALAGONIA
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Patent number: 6333546Abstract: An electrically activated fuse with a high melting point heater element in series with a low melting point fusible link. The heater element has a higher resistivity and larger cross-sectional area than the fusible link in order to withstand heat that the heater element generates bringing the fusible link to its melting point. Fuse dimensions (width and length) are each between 0.1 and 2.0 microns, with a thermal mass of the heater element being sufficient to melt the fusible link.Type: GrantFiled: October 20, 2000Date of Patent: December 25, 2001Assignee: International Business Machines CorporationInventors: Patricia Marmillion, Anthony M. Palagonia, Dennis A. Schmidt
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Patent number: 6294453Abstract: An electrically activated fuse with a high melting point heater element in series with a low melting point fusible link. The heater element has a higher resistivity and larger cross-sectional area than the fusible link in order to withstand heat that the heater element generates bringing the fusible link to its melting point. Fuse dimensions (width and length) are each between 0.1 and 2.0 microns, with a thermal mass of the heater element being sufficient to melt the fusible link.Type: GrantFiled: May 7, 1998Date of Patent: September 25, 2001Assignee: International Business Machines Corp.Inventors: Patricia E. Marmillion, Anthony M. Palagonia, Dennis A. Schmidt
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Patent number: 6171436Abstract: Disclosed is a method and apparatus for polishing a semiconductor wafer. This invention describes a novel in situ method for eliminating residual slurry and slurry abrasive particles on the wafer. A reactant is added to the slurry during the end of the Chemical Mechanical Polish (CMP) process to dissolve the slurry and etch the abrasive particles.Type: GrantFiled: January 8, 1998Date of Patent: January 9, 2001Assignee: International Business Machines CorporationInventors: Cuc K. Huynh, Harold G. Linde, Patricia E. Marmillion, Anthony M. Palagonia, Bernadette A. Pierson, Matthew J. Rutten
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Patent number: 6160302Abstract: A structure (and method) for selectively making an electrical connection comprising a conductive element, wherein the conductive element becomes non-conductive after application of radiation energy, and a reflective element, positioned adjacent at least two sides of the conductive element for reflecting the radiation energy.Type: GrantFiled: August 31, 1998Date of Patent: December 12, 2000Assignee: International Business Machines CorporationInventor: Anthony M. Palagonia
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Patent number: 6050326Abstract: A heat dissipation apparatus for cooling one or more electronic devices. The apparatus utilizes a moving heat sink a portion of which is in contact with the device to be cooled. The moving heat sink may be in the form of a rotating disk, moving belt or strip. The heat sink may be made from various materials such as metals or plastics.Type: GrantFiled: May 12, 1998Date of Patent: April 18, 2000Assignee: International Business Machines CorporationInventors: Richard J. Evans, David L. Gardell, Anthony M. Palagonia
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Patent number: 6037661Abstract: A semiconductor device which includes a first semiconductor chip mounted on top of a lead frame which is molded within a plastic body. During the molding process a cavity is formed on the bottom of the lead frame. After testing or burn-in of the first chip a second semiconductor chip is mounted and electrically connected to the lead frame. The second chip may then be sealed within the cavity to form a multichip module.Type: GrantFiled: December 20, 1996Date of Patent: March 14, 2000Assignee: International Business MachinesInventors: Anthony M. Palagonia, John E. Cronin
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Patent number: 5944588Abstract: A chemical, mechanical polisher having a plurality of cylindrical rollers rotating orthogonally to a rotating work piece that they wipe and cover that are conditioned to uniformly receive a cleaning agent for polishing the work piece.Type: GrantFiled: June 25, 1998Date of Patent: August 31, 1999Assignee: International Business Machines CorporationInventors: Patricia M. Marmillion, Anthony M. Palagonia
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Patent number: 5934977Abstract: A planarizing system which significantly reduces the problems associated with non-uniform removal of surface material across the face of a semiconductor wafer or other comparable workpiece. The invention involves a planarizing apparatus that takes the leading edge of a wafer out of contact with the polishing pad while concomitantly enhancing slurry penetration and distribution at the polishing pad-wafer interface. This result is accomplished by combining: means for deflecting upward a portion of a flexible polishing pad as it passes in rotation beneath a wafer to form a raised polishing pad area, and means for positioning the wafer such that the wafer's leading edge overhangs the front edge of the raised polishing pad area during the planarization procedure. The invention also encompasses a method of using the planarizing apparatus to uniformly remove surface material across the face of a wafer.Type: GrantFiled: June 19, 1997Date of Patent: August 10, 1999Assignee: International Business Machines CorporationInventors: Patricia E. Marmillion, Anthony M. Palagonia
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Patent number: 5896870Abstract: Disclosed is a method and apparatus for polishing a semiconductor wafer. This invention describes a novel in situ method for eliminating residual slurry and slurry abrasive particles on the wafer. A reactant is added to the slurry during the end of the Chemical Mechanical Polish (CMP) process to dissolve the slurry and etch the abrasive particles.Type: GrantFiled: March 11, 1997Date of Patent: April 27, 1999Assignee: International Business Machines CorporationInventors: Cuc K. Huynh, Harold G. Linde, Patricia E. Marmillion, Anthony M. Palagonia, Bernadette A. Pierson, Matthew J. Rutten
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Patent number: 5785584Abstract: A planarizing system which significantly reduces the problems associated with non-uniform removal of surface material across the face of a semiconductor wafer or other comparable workpiece. The invention involves a planarizing apparatus that takes the leading edge of a wafer out of contact with the polishing pad while concomitantly enhancing slurry penetration and distribution at the polishing pad-wafer interface. This result is accomplished by combining: means for deflecting upward a portion of a flexible polishing pad as it passes in rotation beneath a wafer to form a raised polishing pad area, and means for positioning the wafer such that the wafer's leading edge overhangs the front edge of the raised polishing pad area during the planarization procedure. The invention also encompasses a method of using the planarizing apparatus to uniformly remove surface material across the face of a wafer.Type: GrantFiled: August 30, 1996Date of Patent: July 28, 1998Assignee: International Business Machines CorporationInventors: Patricia E. Marmillion, Anthony M. Palagonia
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Patent number: 5604377Abstract: A packaging scheme for a stack of semiconductor chips that is light weight and has better cooling and mechanical and electrical protection than that hitherto provided for. The stack of semiconductor chips are connected to a wiring interface. Separating each of the chips from any adjacent chip is a supporting, insulating interposer. Each interposer electrically insulates each chip from any adjacent chip while mechanically protecting the chip supported thereby. The interposers are the cantilevered shelves of a rack and they prevent undue mechanical movement of the chips while still permitting for convection cooling of the chips. An hermetically sealed enclosure around the stack of chips, can be provided with a cooling fluid therein and completes the package. In another arrangement, the rack is itself is provided with circuitry which may be coupled to the chips positioned and supported therein.Type: GrantFiled: October 10, 1995Date of Patent: February 18, 1997Assignee: International Business Machines Corp.Inventor: Anthony M. Palagonia