Abstract: The present invention is an N-nary equality comparator that receives as inputs two 32-bit 1-of-4 operands. The equality comparator generates an "equal" indicator if the values of the two operands are equal. The equality comparator generates a "not equal" indicator if the values of the two operands are not equal.

Abstract: The present invention comprises a logic device with improved capacitance isolation and a design methodology for reducing unwanted parasitic capacitance in logic circuits. The logic device further comprises an output signal having a first internal evaluate node and a second evaluate node. Additionally, the logic device comprises a first input signal that has a first input wire and a second input wire where the first input wire corresponds to a first possible value of the first input signal and the second input wire corresponds to a second possible value of the first input signal. The logic device further comprises a first plurality of intermediate nodes that includes a first intermediate node. Additionally, the logic device includes a first plurality of transistors that further includes a first transistor coupling the first internal evaluate node to the first intermediate node and being gated by the first wire of the first input signal.

Abstract: The present invention comprises a plurality of clock signals with an approximately 50% duty cycle and overlapping phases. The phases of the plurality of clocks are such that the phase of an individual clock signal overlaps the phase of an earlier clock signal by an amount equal to the overlap of the phase of the next clock signal. The present invention further comprises a plurality of clocked precharge (CP) logic gates coupled in series. An individual CP logic gate couples to an individual clock signal though the CP logic gate's evaluate device. For the data flow through the individual CP logic gate, the logic gate receives its data input from an earlier CP logic gate in the series and passes to the next CP logic gate in the series. The earlier CP logic gate couples to an earlier phase clock signal, and the next CP logic gate couples to the next phase clock signal.

Abstract: The present invention comprises a method and apparatus for a logic circuit with constant power consumption. The logic circuit comprises a 1 of P first input signal that further comprises a plurality of wires wherein each wire of said plurality of wires has equal capacitive loading. The logic circuit additionally comprises a 1 of Q second input signal that comprises a plurality of wires wherein each wire of said plurality of wires has equal capacitive loading. A logic tree circuit couples to the first input signal and the second input signal. The logic tree circuit generates a result for a 1 of R output signal, which couples to the logic tree circuit. The 1 of R output signal comprises a plurality of wires wherein each wire of said plurality of wires has equal capacitive loading. The power consumption of the logic circuit is independent of the value of the first signal or the second signal, which results in the logic circuit having constant power consumption.

Abstract: The present invention is a method and apparatus for a N-nary logic circuit that comprises a logic tree circuit that couples to a first set of input logic paths, a second set of input logic paths, and a set of output logic paths, which all use 1 of N signals where one and only one of the N logic paths is active during an evaluation cycle. The preferred embodiment of the present invention uses 1 of 4 signals, while other embodiments of present invention include 1 of 2 signals, 1 of 3 signals, 1 of 8 encoding, and the general embodiment of the 1 of N signals. The logic tree circuit evaluates a given function that includes, for example, an AND/NAND function, an OR/NOR function, or an XOR/Equivalence function. The logic tree circuit uses a single, shared logic tree with multiple evaluation paths for evaluating the function of the logic circuit.

Abstract: The present invention is a method and apparatus for a N-nary logic circuit that comprises a logic tree circuit that couples to a first set of input logic paths, a second set of input logic paths, and a set of output logic paths, which all use 1 of N signals where one and only one of the N logic paths is active during an evaluation cycle. The preferred embodiment of the present invention uses 1 of 4 signals, while other embodiments of present invention include 1 of 2 signals, 1 of 3 signals, 1 of 8 encoding, and the general embodiment of the 1 of N signals. The logic tree circuit evaluates a given function that includes, for example, an AND/NAND function, an OR/NOR function, or an XOR/Equivalence function. The logic tree circuit uses a single, shared logic tree with multiple evaluation paths for evaluating the function of the logic circuit.

Abstract: A superscalar microprocessor implements a repeated string instruction by putting the microcode unit in a continuous loop. The microcode sequence that implements the repeated string operation includes a conditional-exit instruction rather than a conditional branch and decrement microcode instruction. A conditional-exit instruction decrements a loop count value and conveys a termination signal to a microcode unit when a termination condition is detected. Because several iterations of the instructions that implement the string instruction may be dispatched before the conditional-exit instruction is evaluated, the additional iterations of the microcode loop are canceled. By eliminating the conditional branch and decrement microcode instruction, a loop iteration may be executed in a single clock cycle by three functional units.