Abstract: A method and apparatus for testing or diagnosing memories in an integrated circuit using memory BIST (built-in self-test) or memory scan techniques. The present invention comprises using a data generator in a BIST memory or scan memory to detect or locate coupling faults between any two bits in any memory word in each memory. It includes an address re-mapping logic in the address generator to disable all defective memory banks and to allow the integrated circuit to continue operation but at a reduced memory size. The present invention includes memory selectors one for each memory to perform memory BIST or memory scan in parallel sessions so as to optimize overall test cost and reduce peak power consumption and average power dissipation to an acceptable level. Computer-aided design (CAD) systems are further developed to synthesize the hierarchical memory BIST controller and hierarchical memory scan controller.