Abstract: A method for predicting processor inactivity for a controlled transition of power states. The method of one embodiment comprises predicting a first event that allows for lower performance in a processor. The processor is transitioned from a high performance state to a low performance state upon prediction of the first event. A second event that can utilize greater performance in the processor is detected. The processor is transitioned from the low performance state to the high performance state upon detection of the second event.

Abstract: A multi-processor cache control system wherein cache control information is encoded into the address bits of a memory access request. The encoded cache control information is used to optimize cache control functions. Each memory access request is comprised of at least two elements. First, an address field is provided to define the location of the desired data item. Secondly, cache control information is provided in a cache control field within each memory access request. The cache control field comprises a plurality of bits that define a relationship between the address field and a plurality of local caches associated with processors in a multi-processor system. This relationship determines which of a plurality of local caches may cache the data item referenced by the address within the address field.

Abstract: Components of a computer system are coupled using a data path application specific integrated circuit (ASIC) crossbar switch. A plurality of multi-bit bi-directional register ports are intercoupled using multi-bit multiplexer circuitry. Port selection control signals provided to the multiplexer direct the flow of data through the data path ASIC. The data path ASIC electrically isolates the components of the computer system, thereby minimizing the capacitive load on signal lines and permitting signals to transfer at high rates of speed. Control of the data path ASIC is provided by external circuitry to increase the flexibility of the crossbar switch by removing dependency on any particular communications protocol. Multiple data path ASICs may be combined in parallel to increase bandwidth of data flow by using a bit slice scheme.

Abstract: A processor and a memory address bus, a processor and a memory data bus, and a data transfer control unit are provided to a multiprocessor computer system comprising a first and a second processor, a first and a second corresponding private cache, a pipelined memory shared among the processors, an I/O device, and a cache coherency mechanism for maintaining cache coherency. I/O data stored in the shared memory are cacheable in the private caches. The processor and memory address and data buses are advantageously used to couple these elements and to control data transfers in and out of the shared memory. All data transfers in and out of the shared memory are made in multiples of the basis on which cache coherency is maintained, and through the data transfer control unit.

Abstract: Components of a computer system are coupled using a data path application specific integrated circuit (ASIC) crossbar switch. A plurality of multi-bit bi-directional register ports are intercoupled using multi-bit multiplexer circuitry. Port selection control signals provided to the multiplexer direct the flow of data through the data path ASIC. The data path ASIC electrically isolates the components of the computer system, thereby minimizing the capacitive load on signal lines and permitting signals to transfer at high rates of speed. Control of the data path ASIC is provided by external circuitry to increase the flexibility of the crossbar switch by removing dependency on any particular communications protocol. Multiple data path ASICs may be combined in parallel to increase bandwidth of data flow by using a bit slice scheme.