Patents by Inventor Anthony Manicone

Anthony Manicone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8620251
    Abstract: An electronic device includes an adjustable filter with a first filter element, and a second filter element coupled to the first filter element. The second filter element includes a field effect transistor (FET) including a source terminal, a drain terminal, and a gate terminal. The source terminal and the gate terminal are coupled to a reference voltage. A control circuit is coupled to the drain terminal and is configured to apply a control voltage thereto to vary a capacitance between the source and drain terminals to adjust the adjustable filter.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: December 31, 2013
    Assignee: Harris Corporation
    Inventors: Andrew Mui, Anthony Manicone
  • Publication number: 20130203367
    Abstract: An electronic device includes an adjustable filter with a first filter element, and a second filter element coupled to the first filter element. The second filter element includes a field effect transistor (FET) including a source terminal, a drain terminal, and a gate terminal. The source terminal and the gate terminal are coupled to a reference voltage. A control circuit is coupled to the drain terminal and is configured to apply a control voltage thereto to vary a capacitance between the source and drain terminals to adjust the adjustable filter.
    Type: Application
    Filed: February 8, 2012
    Publication date: August 8, 2013
    Applicant: Harris Corporation
    Inventors: Andrew Mui, Anthony Manicone
  • Patent number: 7439810
    Abstract: RF amplifier bias system for TDMA application. A bias circuit (200) is coupled to an RF power amplifier (201) circuit. The bias circuit includes a charge pump/sink circuit (215) a voltage reference circuit (204) and voltage scaling circuit (208, 210, 214). The bias system provides fast response time when transitioning between various bias voltage applied to an FET RF transistor (244).
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: October 21, 2008
    Assignee: Harris Corporation
    Inventors: Anthony Manicone, Matthew Harris
  • Publication number: 20080132180
    Abstract: A system (200) for lossless transmit path antenna switching in a transceiver using quadrature combined power amplifiers is provided. The system is comprised of a quadrature (90°) hybrid power combiner (218) having a first and a second input port (260, 264), an isolated port (266), and an output port (262). The system is also comprised of a first and second RF power amplifier circuit (212, 214). The RF power amplifier circuits are respectively coupled to the first and second input ports. The RF power amplifier circuits have an output impedance that is selectively variable between a first state and a second state. The quadrature hybrid power combiner communicates RF energy from the first and second input ports to the output port when each RF power amplifier circuit is in its first state. The quadrature hybrid power combiner communicates RF energy from the output port to the isolated port when each RF amplifier circuit is in its second state.
    Type: Application
    Filed: December 1, 2006
    Publication date: June 5, 2008
    Applicant: HARRIS CORPORATION
    Inventor: Anthony Manicone
  • Patent number: 7355854
    Abstract: An apparatus for improved grounding and heat transfer between flange mount field effect transistors and printed wiring boards is provided comprising a cut-out formed in the printed wiring board, extending between its top and bottom surfaces, defining an edge which is covered or plated with a conductive material at least in some areas. One or more vias also extend between the top and bottom surfaces of the cut-out and are exposed along the edge. A field effect transistor is placed in the cut-out and into contact with a heat sink element designed to enhance grounding of the field effect transistor and improve the transfer of heat to the chassis or other metal support structure for the printed wiring board.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: April 8, 2008
    Assignee: Harris Corporation
    Inventors: Matthew Harris, Anthony Manicone
  • Publication number: 20070285172
    Abstract: RF amplifier bias system for TDMA application. A bias circuit (200) is coupled to an RF power amplifier (201) circuit. The bias circuit includes a charge pump/sink circuit (215), a voltage reference circuit (204) and voltage scaling circuit (208, 210, 214). The bias system provides fast response time when transitioning between various bias voltages applied to an FET RF transistor (244).
    Type: Application
    Filed: June 8, 2006
    Publication date: December 13, 2007
    Applicant: Harris Corporation
    Inventors: Anthony Manicone, Matthew Harris
  • Publication number: 20070285893
    Abstract: An apparatus for improved grounding and heat transfer between flange mount field effect transistors and printed wiring boards is provided comprising a cut-out formed in the printed wiring board, extending between its top and bottom surfaces, defining an edge which is covered or plated with a conductive material at least in some areas. One or more vias also extend between the top and bottom surfaces of the cut-out and are exposed along the edge. A field effect transistor is placed in the cut-out and into contact with a heat sink element designed to enhance grounding of the field effect transistor and improve the transfer of heat to the chassis or other metal support structure for the printed wiring board.
    Type: Application
    Filed: June 7, 2006
    Publication date: December 13, 2007
    Inventors: Matthew Harris, Anthony Manicone
  • Publication number: 20070182512
    Abstract: The present invention provides a method and apparatus for design of low loss, size restricted high frequency circuits. In a preferred embodiment, an electronic device includes: a first circuit layer located above the main circuit board comprising a first stripline passive circuit; and a second circuit layer located above the first circuit, the second layer comprising a second stripline circuit. The two stripline circuits can be separately coupled to leads, or coupled to each other and other leads using vias through the ground layer(s) separating each stripline. The stacked stripline elements can be used together with other circuits, and the stacked circuit board can be conveniently joined together with other assemblies, e.g., by surface mounting to a main board. The utility of this topology can be extended by the use of n-circuit embodiment or embedding in a multilayered main circuit board.
    Type: Application
    Filed: February 7, 2006
    Publication date: August 9, 2007
    Inventors: Myung Lee, Anthony Manicone