Abstract: A symbol synchronizer, as for use with apparatus for detecting MPSK signals to provide complex sampled data descriptive of keying signal phase, in which the timing of the resampling can be controlled with resolution that is a fraction of the time between successive complex data samples.The symbol synchronizer uses a first digital controlled oscillator to recover the MPSK baseband signal sampled at a frequency f.sub.i rate. The MPSK signal is operated on to recover a sampled data description of the envelope of the MPSK signal sampled at a frequency f.sub.s, which may equal f.sub.i or be down-sampled therefrom. This is digitally filtered to provide a sampled data locking signal to a second digital controlled oscillator, which uses modular arithmetic to generate a digital sampled data description at f.sub.s rate of a sawtooth waveform repetitive at f.sub.k keying rate. In this second digital-controlled oscillator an adder sums its output as delayed by a full f.sub.

Abstract: Oscillators phase locked to transitions in the envelope of a bandwidth-limited complex waveform are used, for example, in detecting MPSK signals. The magnitude of the envelope is approximated by linearly combining the real and imaginary components of the complex waveform, or by selecting the larger of the two components, or by using both these techniques in combination.

Abstract: A method and apparatus for the adaptive equalizing of phase and amplitude distortion in a received signal by an N-stage digital delay line system and comprising the steps of digitally sampling the received signal and advancing each digital sample through successive stages of the N-stage digital delay line, producing a continuously up-dated scaled error signal after each advance of the digital samples in the delay line, multiplying the digital sample in each delay line stage by the scaled error signal after each sampling advance to produce a first scaled signal in each stage, separately accumulating the first scaled signals of each stage after each sampling advance, scaling and accumulating the accumulations of the first scaled signals of each stage after each M accumulations thereof to produce a weighting tap signal for each stage of the delay line, multiplying the received samples by the weighting tap signal of each stage to produce a weighted sampling for each stage, summing the weighted samplings to produc

Abstract: A digital linear phase shift convolutional filter for filtering a series of binary number electrical signals each of which represents the magnitude of a sample of an analog electrical signal sampled at a predetermined rate. The convolutional filter utilizes a bidirectional shift register and a preferably unidirectional shift register. Each of the registers has a plurality of stages. The bidirectional shift register receives the serially presented binary number electrical signals representative of the sample magnitudes, and these samples are sequentially transferred from the output stage of the bidirectional shift register to the input stage of the unidirectional shift register.

Abstract: A circuit for transforming to polar coordinate form first and second binary number electrical signals representative of rectangular coordinates or quadrature components for a vector or phasor. The circuit utilizes a programmable memory in which values corresponding to the sine and cosine functions are stored. In the preferred form, the circuit utilizes binary number electrical signals of 10 bits. The most significant bit of the polar coordinate angle is found directly from the binary number representing one of the quadrature components, whereas the next two most significant bits of the angle are found using logic circuitry in association with the binary number signals representing the quadrature components. The remaining bits of the angle are found by use of a successive approximation technique in conjunction with the values stored in the memory. Once the angle is determined, the amplitude of the vector or phasor is determined by the use of the function P = Im(sin.theta.) + Re(cos.theta.

Abstract: A digital click removal and squelch control circuit for a digital FM receiver. The digital receiver generates a series of binary number electrical signals each of which is representative of the instantaneous phase angle of a received frequency-modulated electrical signal or signal derived therefrom. The phase angle signals are differentiated to produce binary number electrical signals that represent the rate of change of phase angle, or, the instantaneous frequency of the received signal. During a given time interval, the phase change caused by the modulation of the received signal must be within a range determined by the bandwidth of the received frequency-modulated signal. Phase changes outside of this range represent electrical noise or clicks and are removed by the click removal circuit of the invention.