Abstract: A switched capacitor circuit (10) is responsive to a two phase repetitive clock signal comprised of alternating periods (.phi.1) and (.phi.2). The circuit includes a first input branch including a first amplifier (A) for charging a first capacitance (C1) from a first input signal during period (.phi.2). The circuit further includes a second input branch that includes a second amplifier (B) for charging a second capacitance (CA) from a second input signal during a period (.phi.1A), and for charging a third capacitance (CB) from the second input signal during a period (.phi.1B); wherein (.phi.1A) and (.phi.1B) alternate in occurrence with one another during successive (.phi.1) periods. The circuit further includes switches for coupling the first capacitance and the second capacitance to an input of an output amplifier (C) during (.phi.1B), and for coupling the first capacitance and the third capacitance to the input of the output amplifier during (.phi.1A).

Abstract: A multi-bit cascaded sigma-delta A/D converter (40) has a higher resolution, higher sample rate, and lower harmonic distortion than previous multi-bit cascaded sigma-delta approaches. The A/D converter employs delaying switched capacitor integrators to relax settling time requirements and to thereby ease op amp design for multi-bit cascaded sigma-delta A/D converters. The converter has a true sample and hold input; the op amp amplifies a fixed amount of charge; and nodes are settled with the dc gain of the op amp, permitting greater settling accuracy.