Abstract: A computer system comprising a processor and a memory for storing instructions, that when executed by the processor performs a copy protection method. The copy protection method comprises executing a software loop of a first software application in a first operating system. A first call is executed in the software loop to a code portion. A decrypted code portion of the first software application is executed in a second operating system in response to the first call. The code portion is decrypted in response to a successful validation of the first software application.

Abstract: A computer system comprising a processor and a memory for storing instructions, that when executed by the processor performs a copy protection method. The copy protection method comprises executing a software loop of a first software application in a first operating system. A first call is executed in the software loop to a code portion. A decrypted code portion of the first software application is executed in a second operating system in response to the first call. The code portion is decrypted in response to a successful validation of the first software application.

Abstract: A computer system comprising a processor and a memory for storing instructions, that when executed by the processor performs a copy protection method. The copy protection method comprises executing a software loop of a first software application in a first operating system. A first call is executed in the software loop to a code portion. A decrypted code portion of the first software application is executed in a second operating system in response to the first call. The code portion is decrypted in response to a successful validation of the first software application.

Abstract: A method for optimizing a user's experience. The method includes detecting a newly discovered gaming application on a computing device, and receiving an instruction to optimize the newly discovered gaming application. The method includes determining a hardware configuration for the computing device. The method includes accessing pre-defined optimal settings based on the gaming application and the hardware configuration, and writing the pre-defined optimal settings into a game settings file associated with the gaming application.

Abstract: Circuits, methods, and apparatus for modifying the data rate of a data bus. In a circuit having two processors coupled by a data bus, the processors each learn that the other is capable of operating at a modified data rate. The data rate is then changed to the modified rate. Each processor may learn of the other's capability by reading a vendor identification, for example from a vendor defined message stored on the other processor. Alternately, each processor may provide an instruction to the other to operate at the modified rate, for example by writing to the other processor's extended capability registers. In another circuit having two processors communicating over a bus, it is determined that both are capable of transmitting and receiving data at a modified data rate. An instruction is provided to one or both of the processors to transmit at the modified rate.

Abstract: A method and system for a cooperative graphics processing across a graphics bus in a computer system. The system includes a bridge coupled to a system memory via a system memory bus and coupled to a graphics processor via the graphics bus. The bridge includes a fragment processor for implementing cooperative graphics processing with the graphics processor coupled to the graphics bus. The fragment processor is configured to implement a plurality of raster operations on graphics data stored in the system memory.

Abstract: Circuits, methods, and apparatus for modifying the data rate of a data bus. In a circuit having two processors coupled by a data bus, the processors each learn that the other is capable of operating at a modified data rate. The data rate is then changed to the modified rate. Each processor may learn of the other's capability by reading a vendor identification, for example from a vendor defined message stored on the other processor. Alternately, each processor may provide an instruction to the other to operate at the modified rate, for example by writing to the other processor's extended capability registers. In another circuit having two processors communicating over a bus, it is determined that both are capable of transmitting and receiving data at a modified data rate. An instruction is provided to one or both of the processors to transmit at the modified rate.

Abstract: A gaming console including a housing configured for handheld manipulation. A processor is contained within the housing and configured for executing a gaming application. Memory is contained within the housing and configured for storing executables of the gaming application. At least one control button is exposed on the housing and is configured for receiving input from a user that provides an instruction for the gaming application. The gaming console includes a high definition (HD) display for displaying the gaming application.

Abstract: One or more embodiments of the present invention may include a body comprising a user interface, wherein the user interface is operable to be configured for a first interactive media device and a second interactive media device. The one or more embodiments may further include memory operable to store a plurality of user interface configurations, wherein a first user interface configuration corresponds to the first interactive media device and the second interactive media device, and wherein the memory is further operable to store a software application state. The one or more embodiments may additionally include a communication interface operable to communicatively couple with the first interactive media device and the second interactive media device, wherein the communication interface is operable to send user inputs from the user interface to the first interactive media device and the second interactive media device.

Abstract: A system for compressed data transfer across a graphics bus in a computer system. The system includes a bridge, a system memory coupled to the bridge, and a graphics bus coupled to the bridge. A graphics processor is coupled to the graphics bus. The graphics processor is configured to compress graphics data and transfer compressed graphics data across the graphics bus to the bridge for subsequent storage in the system memory.

Abstract: The present invention pertains to a configurable PCI-Express switch. The configurable PCI-Express switch includes a differential I/O interface capable of being configured in a first configuration or a second configuration. In the first configuration, the differential I/O interface implements a PCI-Express interface with a coupled device. In the second configuration, the differential I/O interface implements a differential interface other than PCI-Express with the coupled device. The configurable PCI-Express switch also includes a switching unit capable of configuring the differential I/O interface in the first configuration or the second configuration.

Abstract: The present invention pertains to a graphics processing unit. The graphics processing unit includes a graphics processing core configured for graphics processing. A single-ended I/O interface configured to implement single-ended communication with a frame buffer memory is included in the graphics processing unit. The graphics processing unit further includes a differential I/O interface having a first portion and a second portion. In a first configuration, the first portion and the second portion implement a PCI-Express interface with a computer system. In a second configuration, the first portion implements a PCI-Express interface with the computer system and the second portion implements differential communication with a coupled device.

Abstract: A computer system comprising a processor and a memory for storing instructions, that when executed by the processor performs a copy protection method. The copy protection method comprises executing a software loop of a first software application in a first operating system. A first call is executed in the software loop to a code portion. A decrypted code portion of the first software application is executed in a second operating system in response to the first call. The code portion is decrypted in response to a successful validation of the first software application.

Abstract: A memory hub permits a graphics processor to access random access memories, such as dynamic random access memories (DRAMs). In one implementation, the memory hub permits an increase in effective memory bandwidth by aggregating the memory of two or more memories. In another implementation, the memory hub permits a graphics processor to offload memory access interfacing operations to the memory hub.

Abstract: A system for implementing handshaking configuration to enable coordinated data execution in a computer system. The system includes a core logic component coupled to a system memory and a graphics processor coupled to the core logic component via a graphics bus. The graphics processor and the core logic component implement a configuration communication to selectively configure coordinated data execution between the graphics processor and the core logic component via communication across the graphics bus.

Abstract: In a graphics processor, a rendering object and a post-processing object share access to a host processor with a programmable execution core. The rendering object generates fragment data for an image from geometry data. The post-processing object operates to generate a frame of pixel data from the fragment data and to store the pixel data in a frame buffer. In parallel with operations of the host processor, a scanout engine reads pixel data for a previously generated frame and supplies the pixel data to a display device. The scanout engine periodically triggers the host processor to operate the post-processing object to generate the next frame. Timing between the scanout engine and the post-processing object can be controlled such that the next frame to be displayed is ready in a frame buffer when the scanout engine finishes reading a current frame.

Abstract: A memory hub permits a graphics processor to access random access memories, such as dynamic random access memories (DRAMs). In one implementation, the memory hub permits an increase in effective memory bandwidth by aggregating the memory of two or more memories. In another implementation, the memory hub permits a graphics processor to offload memory access interfacing operations to the memory hub.

Abstract: A memory hub permits a graphics processor to access random access memories, such as dynamic random access memories (DRAMs). In one implementation, the memory hub permits an increase in effective memory bandwidth by aggregating the memory of two or more memories. In another implementation, the memory hub permits a graphics processor to offload memory access interfacing operations to the memory hub.