Patents by Inventor Anthony Moschopoulos
Anthony Moschopoulos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8959295Abstract: Bit inversions occurring in memory systems and apparatus are provided. Data is acquired from a source destined for a target. As the data is acquired from the source, the set bits associated with data are tabulated. If the total number of set bits exceeds more than half of the total bits, then an inversion flag is set. When the data is transferred to the target, the bits are inverted during the transfer if the inversion flag is set. Alternatively, an acquired data stream includes an association with an inversion bit. The inversion bit is acquired and stored separately from the data stream. As the data stream is transferred, if the inversion bit is set then the stream is inverted during the transfer of the stream to a target.Type: GrantFiled: November 25, 2013Date of Patent: February 17, 2015Assignee: Micron Technology, Inc.Inventor: Anthony Moschopoulos
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Patent number: 8792277Abstract: Split data error correction code (ECC) circuits including a control circuit coupled to an error correction code (ECC) circuit. The ECC circuit is adapted to generate at least one ECC code from user data of a first physical sector during a data access. The split data ECC circuit is adapted to write the at least one ECC code to a second physical sector if the data access is a write access and to compare the at least one generated ECC code with at least one ECC code stored in a second physical sector if the data access is a read access.Type: GrantFiled: September 16, 2013Date of Patent: July 29, 2014Assignee: Micron Technology, Inc.Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady L. Keays
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Publication number: 20140089571Abstract: Bit inversions occurring in memory systems and apparatus are provided. Data is acquired from a source destined for a target. As the data is acquired from the source, the set bits associated with data are tabulated. If the total number of set bits exceeds more than half of the total bits, then an inversion flag is set. When the data is transferred to the target, the bits are inverted during the transfer if the inversion flag is set. Alternatively, an acquired data stream includes an association with an inversion bit. The inversion bit is acquired and stored separately from the data stream. As the data stream is transferred, if the inversion bit is set then the stream is inverted during the transfer of the stream to a target.Type: ApplicationFiled: November 25, 2013Publication date: March 27, 2014Applicant: Micron Technology, Inc.Inventor: Anthony Moschopoulos
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Publication number: 20140019826Abstract: Split data error correction code (ECC) circuits including a control circuit coupled to an error correction code (ECC) circuit. The ECC circuit is adapted to generate at least one ECC code from user data of a first physical sector during a data access. The split data ECC circuit is adapted to write the at least one ECC code to a second physical sector if the data access is a write access and to compare the at least one generated ECC code with at least one ECC code stored in a second physical sector if the data access is a read access.Type: ApplicationFiled: September 16, 2013Publication date: January 16, 2014Applicant: Micron Technology, Inc.Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays
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Patent number: 8612695Abstract: Bit inversions occurring in memory systems and apparatus are provided. Data is acquired from a source destined for a target. As the data is acquired from the source, the set bits associated with data are tabulated. If the total number of set bits exceeds more than half of the total bits, then an inversion flag is set. When the data is transferred to the target, the bits are inverted during the transfer if the inversion flag is set. Alternatively, an acquired data stream includes an association with an inversion bit. The inversion bit is acquired and stored separately from the data stream. As the data stream is transferred, if the inversion bit is set then the stream is inverted during the transfer of the stream to a target.Type: GrantFiled: July 31, 2012Date of Patent: December 17, 2013Assignee: Micron Technology, Inc.Inventor: Anthony Moschopoulos
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Patent number: 8537614Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.Type: GrantFiled: May 16, 2011Date of Patent: September 17, 2013Assignee: Micron Technology, Inc.Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays
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Publication number: 20120297153Abstract: Bit inversions occurring in memory systems and apparatus are provided. Data is acquired from a source destined for a target. As the data is acquired from the source, the set bits associated with data are tabulated. If the total number of set bits exceeds more than half of the total bits, then an inversion flag is set. When the data is transferred to the target, the bits are inverted during the transfer if the inversion flag is set. Alternatively, an acquired data stream includes an association with an inversion bit. The inversion bit is acquired and stored separately from the data stream. As the data stream is transferred, if the inversion bit is set then the stream is inverted during the transfer of the stream to a target.Type: ApplicationFiled: July 31, 2012Publication date: November 22, 2012Inventor: Anthony Moschopoulos
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Patent number: 8239636Abstract: Bit inversions occurring in memory systems and apparatus are provided. Data is acquired from a source destined for a target. As the data is acquired from the source, the set bits associated with data are tabulated. If the total number of set bits exceeds more than half of the total bits, then an inversion flag is set. When the data is transferred to the target, the bits are inverted during the transfer if the inversion flag is set. Alternatively, an acquired data stream includes an association with an inversion bit. The inversion bit is acquired and stored separately from the data stream. As the data stream is transferred, if the inversion bit is set then the stream is inverted during the transfer of the stream to a target.Type: GrantFiled: July 27, 2006Date of Patent: August 7, 2012Assignee: Micron Technology, Inc.Inventor: Anthony Moschopoulos
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Publication number: 20110219178Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.Type: ApplicationFiled: May 16, 2011Publication date: September 8, 2011Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays
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Patent number: 7944748Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.Type: GrantFiled: May 21, 2009Date of Patent: May 17, 2011Assignee: Micron Technology, Inc.Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays
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Publication number: 20090225606Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.Type: ApplicationFiled: May 21, 2009Publication date: September 10, 2009Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays
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Patent number: 7549011Abstract: Bit inversions occurring in memory systems and apparatus are provided. Data is acquired from a source destined for a target. As the data is acquired from the source, the set bits associated with data are tabulated. If the total number of set bits exceeds more than half of the total bits, then an inversion flag is set. When the data is transferred to the target, the bits are inverted during the transfer if the inversion flag is set.Type: GrantFiled: August 30, 2001Date of Patent: June 16, 2009Assignee: Micron Technology, Inc.Inventor: Anthony Moschopoulos
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Patent number: 7545682Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.Type: GrantFiled: July 19, 2006Date of Patent: June 9, 2009Assignee: Micron Technology, Inc.Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays
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Patent number: 7480762Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.Type: GrantFiled: May 2, 2005Date of Patent: January 20, 2009Assignee: Micron Technology, Inc.Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays
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Patent number: 7193899Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.Type: GrantFiled: December 3, 2004Date of Patent: March 20, 2007Assignee: Micron Technology, Inc.Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays
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Publication number: 20060259716Abstract: Bit inversions occurring in memory systems and apparatus are provided. Data is acquired from a source destined for a target. As the data is acquired from the source, the set bits associated with data are tabulated. If the total number of set bits exceeds more than half of the total bits, then an inversion flag is set. When the data is transferred to the target, the bits are inverted during the transfer if the inversion flag is set. Alternatively, an acquired data stream includes an association with an inversion bit. The inversion bit is acquired and stored separately from the data stream. As the data stream is transferred, if the inversion bit is set then the stream is inverted during the transfer of the stream to a target.Type: ApplicationFiled: July 27, 2006Publication date: November 16, 2006Inventor: Anthony Moschopoulos
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Publication number: 20060256624Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.Type: ApplicationFiled: July 19, 2006Publication date: November 16, 2006Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays
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Publication number: 20050190599Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.Type: ApplicationFiled: May 2, 2005Publication date: September 1, 2005Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays
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Patent number: 6906961Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.Type: GrantFiled: June 24, 2003Date of Patent: June 14, 2005Assignee: Micron Technology, Inc.Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays
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Publication number: 20050099845Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.Type: ApplicationFiled: December 3, 2004Publication date: May 12, 2005Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays