Abstract: Simulation of execution of a processing workload by a target hardware device is provided by providing workload data specifying the processing workload, passing the workload data to both a primary partial simulation and a complementary partial simulation that run in parallel and acquire input data from different levels of abstraction of the target hardware and then simulating execution of the processing workload using a primary partial simulation to generate primary partial result state data and using the complementary partial simulation to generate complementary partial result state data. The target hardware device may be a graphics processing unit and the workload data may specify the processing to be performed in a hardware independent form, such as, for example, OpenGL ES. The host system supporting the simulation may include a graphics processing unit serving to provide the complementary partial simulation due to its own execution of the workload data.

Abstract: Simulation of execution of a processing workload by a target hardware device is provided by providing workload data specifying the processing workload, passing the workload data to both a primary partial simulation and a complementary partial simulation that run in parallel and acquire input data from different levels of abstraction of the target hardware and then simulating execution of the processing workload using a primary partial simulation to generate primary partial result state data and using the complementary partial simulation to generate complementary partial result state data. The target hardware device may be a graphics processing unit and the workload data may specify the processing to be performed in a hardware independent form, such as, for example, OpenGL ES. The host system supporting the simulation may include a graphics processing unit serving to provide the complementary partial simulation due to its own execution of the workload data.

Abstract: An encoding method generates an encoded image according to a predetermined encoding format. The method includes the step of, for each block of pixels, determining an average color of colors of the block of pixels in the predetermined color space; selecting at least one luminance line in dependence on an offset in the color space of the average color from the at least one luminance line; identifying a set of candidate base colors lying on the at least one luminance line; and determining, using the set of candidate base colors and the luminance offset values, the set of encoded pixel colors. The base color and the set of luminance offsets are selected in dependence on an encoding error indicative of a sum distance in the color space between the set of encoded pixel colors and the colors of the block of pixels.

Abstract: An encoding method generates an encoded image according to a predetermined encoding format. The method includes the step of, for each block of pixels, determining an average colour of colours of the block of pixels in the predetermined colour space; selecting at least one luminance line in dependence on an offset in the colour space of the average colour from the at least one luminance line; identifying a set of candidate base colours lying on the at least one luminance line; and determining, using the set of candidate base colours and the luminance offset values, the set of encoded pixel colours. The base colour and the set of luminance offsets are selected in dependence on an encoding error indicative of a sum distance in the colour space between the set of encoded pixel colours and the colours of the block of pixels.

Abstract: The present invention provides a system and method for controlling a simulator to run a software simulation of a data processing system in order to generate simulated timing data indicative of performance of an unmodelled portion of the data processing system not modelled by the software simulation. The software simulation provides a timing accurate model of those parts of the data processing system other than the unmodelled portion. The method of the invention comprises inputting to a controller of the simulator real trace data obtained from execution of a program by the data processing system, the real trace data identifying the sequence of instructions executed by the data processing system, and associated timing data.

Abstract: The present invention relates to a data processing apparatus and method for compiling application code. The data processing apparatus comprises a processor, and a compiler for compiling application code to generate instructions for execution by the processor. Furthermore, a non-invasive trace unit is coupled to the processor for generating, from input signals received from the processor, trace signals indicative of the instructions being executed by the processor. The compiler is then arranged to control the compilation of the application code dependent on the trace signals. The non-invasive nature of the trace unit enables it to generate trace signals that can be used to produce profiling information for use by the compiler without altering the behaviour of the code being executed by the processor, and accordingly provides a significantly improved technique for obtaining profiling information for use in feedback driven optimization compilation techniques.

Abstract: The present invention provides an apparatus and method for facilitating debugging of sequences of processing instructions. The apparatus comprises a processing circuit for executing processing instructions, the processing circuit having multiple states of operation, with each state of operation being assigned a context identifier to identify the state of operation. Further, logic is provided for facilitating debugging of sequences of processing instructions executed by the processing circuit. The logic comprises control logic, responsive to control parameters, to perform predetermined actions to facilitate debugging, and triggering logic for generating the control parameters dependent on data received from the processing circuit indicative of the processing being performed by the processing circuit.

Abstract: The present invention provides a system and method for controlling a simulator to run a software simulation of a data processing system in order to generate simulated timing data indicative of performance of an unmodelled portion of the data processing system not modelled by the software simulation. The software simulation provides a timing accurate model of those parts of the data processing system other than the unmodelled portion. The method of the invention comprises inputting to a controller of the simulator real trace data obtained from execution of a program by the data processing system, the real trace data identifying the sequence of instructions executed by the data processing system, and associated timing data.

Abstract: The present invention relates to a data processing apparatus and method for compiling application code. The data processing apparatus comprises a processor, and a compiler for compiling application code to generate instructions for execution by the processor. Furthermore, a non-invasive trace unit is coupled to the processor for generating, from input signals received from the processor, trace signals indicative of the instructions being executed by the processor. The compiler is then arranged to control the compilation of the application code dependent on the trace signals. The non-invasive nature of the trace unit enables it to generate trace signals that can be used to produce profiling information for use by the compiler without altering the behaviour of the code being executed by the processor, and accordingly provides a significantly improved technique for obtaining profiling information for use in feedback driven optimisation compilation techniques.

Abstract: The present invention provides an apparatus and method for facilitating debugging of sequences of processing instructions. The apparatus comprises a processing circuit for executing processing instructions, the processing circuit having multiple states of operation, with each state of operation being assigned a context identifier to identify the state of operation. Further, logic is provided for facilitating debugging of sequences of processing instructions executed by the processing circuit. The logic comprises control logic, responsive to control parameters, to perform predetermined actions to facilitate debugging, and triggering logic for generating the control parameters dependent on data received from the processing circuit indicative of the processing being performed by the processing circuit.

Abstract: A packet is originated in a unit 10 as a data field DATA 11 plus a CRC (cyclic redundancy check) check field CRC 12 by a CRC circuit 13. This packet has a header HDR (with a routing information field RIF) added to it in a unit 20, converting it into a message for transmission through a message network. A check correction field CCF is computed by unit 23 in unit 20, by looking up precomputed check subfields stored with the routing subfields (the routing information field being constructed by selecting from the stored subfields), such that the CRC field is a valid CRC check field for the complete message. At the destination, unit 30 can be the final user unit, checking the entire message and extracting the data field DATA therefrom; the DATA field does not need to be checked, as the CRC field acts as a check both for the data field DATA alone and the entire message.

Abstract: A packet is originated in a unit 10 as a data field DATA 11 plus a CRC (cyclic redundancy check) check field CRC 12 by a CRC circuit 13. This packet has a header HDR (with a routing information field RIF) added to it in a unit 20, converting it into a message for transmission through a message network. A check correction field CCF is computed by unit 23 in unit 20, by looking up precomputed check subfields stored with the routing subfields (the routing information field being constructed by selecting from the stored subfields), such that the CRC field is a valid CRC check field for the complete message. At the destination, unit 30 can be the final user unit, checking the entire message and extracting the data field DATA therefrom; the DATA field does not need to be checked, as the CRC field acts as a check both for the data field DATA alone and the entire message.