Patents by Inventor Anthony P. Curtis

Anthony P. Curtis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9627254
    Abstract: An exemplary method includes forming a vertical pillar overlying or laterally displaced from a bond pad overlying a semiconductor substrate, and applying a discrete solder sphere in combination with one of a solder paste or flux on a top surface of the pillar, wherein the one of the solder paste or flux is defined by at least one photoresist layer. The method may include applying a solder sphere and/or solder flux in different combinations on top surfaces of different first and second pillars.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 18, 2017
    Inventors: Guy F. Burgess, Anthony P. Curtis, Eugene A. Stout, Theodore G. Tessier, Lillian C. Thompson
  • Publication number: 20150270223
    Abstract: A wafer level semiconductor device and manufacturing method including providing a semiconductor device wafer substitute having a backside, applying to the backside a conductive metallization layer, and applying to the backside over the conductive metallization layer a protective metal layer of titanium, titanium alloys, nickel, nickel alloys, chromium, chromium alloys, cobalt, cobalt alloys, palladium, and palladium alloys.
    Type: Application
    Filed: December 19, 2014
    Publication date: September 24, 2015
    Inventors: Guy F. Burgess, Anthony P. Curtis, Douglas M. Scott, Shannon D. Buzard
  • Patent number: 9070747
    Abstract: Structures and methods provide a dielectric bridge for use in electroplating. A method comprises: providing a semiconductor wafer with a plurality of die, wherein a first die is adjacent to a second die, and the first die and second die are separated by a dicing street area; forming a patterned dielectric layer overlying the semiconductor wafer, the dielectric layer including a dielectric bridge that crosses the dicing street area; forming a conductive layer (e.g., a metal seed layer) overlying the dielectric layer, wherein a portion of the conductive layer is overlying the dielectric bridge to provide a current pathway from the first die to the second die; and electroplating targeted areas of the conductive layer by providing current to the second die using the current pathway. Other such bridges formed from the dielectric layer provide current pathways to other die on the wafer.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: June 30, 2015
    Assignee: Flipchip International LLC
    Inventors: Eugene A. Stout, Douglas M. Scott, Anthony P. Curtis, Theodore G. Tessier, Guy F. Burgess
  • Patent number: 8980743
    Abstract: A wafer level semiconductor device and manufacturing method including providing a semiconductor device wafer substrate having a backside, applying to the backside a conductive metallization layer, and applying to the backside over the conductive metallization layer a protective metal layer of titanium, titanium alloys, nickel, nickel alloys, chromium, chromium alloys, cobalt. cobalt alloys, palladium, and palladium alloys.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: March 17, 2015
    Assignee: FlipChip International LLC
    Inventors: Guy F. Burgess, Shannon D. Buzard, Anthony P. Curtis, Douglas M. Scott
  • Publication number: 20150001684
    Abstract: Structures and methods provide a dielectric bridge for use in electroplating. A method comprises: providing a semiconductor wafer with a plurality of die, wherein a first die is adjacent to a second die, and the first die and second die are separated by a dicing street area; forming a patterned dielectric layer overlying the semiconductor wafer, the dielectric layer including a dielectric bridge that crosses the dicing street area; forming a conductive layer (e.g., a metal seed layer) overlying the dielectric layer, wherein a portion of the conductive layer is overlying the dielectric bridge to provide a current pathway from the first die to the second die; and electroplating targeted areas of the conductive layer by providing current to the second die using the current pathway. Other such bridges formed from the dielectric layer provide current pathways to other die on the wafer.
    Type: Application
    Filed: September 27, 2013
    Publication date: January 1, 2015
    Applicant: FlipChip International, LLC
    Inventors: Eugene A. Stout, Douglas M. Scott, Anthony P. Curtis, Theodore G. Tessier, Guy F. Burgess
  • Publication number: 20130328203
    Abstract: A wafer level semiconductor device and manufacturing method including providing a semiconductor device wafer substrate having a backside, applying to the backside a conductive metallization layer, and applying to the backside over the conductive metallization layer a protective metal layer of titanium, titanium alloys, nickel, nickel alloys, chromium, chromium alloys, cobalt or cobalt alloys, tungsten or tungsten alloys and palladium or palladium alloys.
    Type: Application
    Filed: March 7, 2013
    Publication date: December 12, 2013
    Applicant: FlipChip International, LLC
    Inventors: Guy F. Burgess, Shannon D. Buzard, Anthony P. Curtis, Douglas M. Scott
  • Patent number: 8058163
    Abstract: A method and device for enhanced reliability for semiconductor devices using dielectric encasement is disclosed. The method and device are directed to improving the reliability of the solder joint that connects the integrated circuit (IC) chip to the substrate. The method comprises applying a layer of a photoimageable permanent dielectric material to a top surface of the semiconductor device, and patterning the layer of the photoimageable permanent dielectric material to have an opening over each feature. The method further comprises dispensing or stencil printing fluxing material into the permanent dielectric material openings, and applying solder, which contains no flux, to a top surface of the fluxing material. In one or more embodiments, the method further comprises heating the semiconductor device to a reflow temperature appropriate for the reflow of the solder, thereby causing the solder to conform to sidewalls of the permanent dielectric material openings to form a protective seal.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: November 15, 2011
    Assignee: Flipchip International, LLC
    Inventors: John J. H. Reche, Michael E. Johnson, Guy F. Burgess, Anthony P. Curtis, Stuart Lichtenthal
  • Publication number: 20100032836
    Abstract: A method and device for enhanced reliability for semiconductor devices using dielectric encasement is disclosed. The method and device are directed to improving the reliability of the solder joint that connects the integrated circuit (IC) chip to the substrate. The method comprises applying a layer of a photoimageable permanent dielectric material to a top surface of the semiconductor device, and patterning the layer of the photoimageable permanent dielectric material to have an opening over each feature. The method further comprises dispensing or stencil printing fluxing material into the permanent dielectric material openings, and applying solder, which contains no flux, to a top surface of the fluxing material. In one or more embodiments, the method further comprises heating the semiconductor device to a reflow temperature appropriate for the reflow of the solder, thereby causing the solder to conform to sidewalls of the permanent dielectric material openings to form a protective seal.
    Type: Application
    Filed: August 6, 2009
    Publication date: February 11, 2010
    Applicant: FLIPCHIP INTERNATIONAL, LLC
    Inventors: John J.H. Reche, Michael E. Johnson, Guy F. Burgess, Anthony P. Curtis, Stuart Lichtenthal