Abstract: A crossbar structure for use in a multi-processor computer system to connect a plurality of processors to at least one shared resource. The crossbar structure comprises for each processor, a storage location for receiving from a respective processor a memory address of a lock control structure associated with the shared resource. When the processor needs to acquire a lock thereto, the crossbar structure, on behalf of the processor, performs memory operations on the lock control structure at the address specified in the storage location in order to acquire the lock on behalf of the processor.

Abstract: A remote monitoring system providing diagnostic and remedial functions to a computer system. The remote monitoring system comprises a service center and a diagnostic agent. The diagnostic agent is located proximate to the monitored computer system and electronically coupled to the monitored computer system such that the diagnostic agent can retrieve information about the various states of the monitored computer system. The diagnostic agent stores the retrieved information and further processes it for future use. Such information includes fault monitor information, accounting information, system performance information, and system management information. In addition, the diagnostic agent has control over the monitored computer system allowing it to perform diagnostic and remedial functions. Further, the diagnostic agent is electronically coupled to a service center located remotely to the monitored computer system.

Abstract: An enhanced cache line directory entry includes at least one affinity bit that indicates an affinity for a particular type of cache line ownership. The affinity bit is used to modify a request for a cache line in accordance with the indicated affinity. The affinity bit may represent an affinity for read-only requests, and the affinity bit may represent an affinity for read-write requests. For example, if an I/O affinity bit is in the set state and an I/O device requests a cache line with read-write permission, the request may be converted to a read-only request in accordance with the indicated affinity. As another example, if a processor affinity bit is in the set state and a processor requests a cache line with read-only permission, the request may be converted to a read-write request. Software control of the affinity bits enables system performance to be tuned and cache coherency operations can thereby be reduced.

Abstract: The invention provides a method, system, and computer-readable medium having computer-executable instructions for designing a PCB using both HDL design elements and schematic design elements. The inventive method comprises the steps of selecting the HDL design elements and selecting the schematic design elements. The inventive method further comprises automatically interconnecting the HDL design elements, and automatically interconnecting the schematic design elements. The PCB is then physically designed based on the interconnected HDL and schematic design elements. The method may further comprise creating a schematic version from the interconnected HDL design elements, and creating a HDL version from the interconnected schematic design elements. The inventive method also may simulate the schematic version of the HDL design elements, and simulate the HDL version of the schematic design elements.

Abstract: An enhanced cache line directory entry includes at least one affinity bit that indicates an affinity for a particular type of cache line ownership. The affinity bit is used to modify a request for a cache line in accordance with the indicated affinity. The affinity bit may represent an affinity for read-only requests, and the affinity bit may represent an affinity for read-write requests. For example, if an I/O affinity bit is in the set state and an I/O device requests a cache line with read-write permission, the request may be converted to a read-only request in accordance with the indicated affinity. As another example, if a processor affinity bit is in the set state and a processor requests a cache line with read-only permission, the request may be converted to a read-write request. Software control of the affinity bits enables system performance to be tuned and cache coherency operations can thereby be reduced.

Abstract: The invention provides a method, system, and computer-readable medium having computer-executable instructions for designing a PCB using both HDL design elements and schematic design elements. The inventive method comprises the steps of selecting the HDL design elements and selecting the schematic design elements. The inventive method further comprises automatically interconnecting the HDL design elements, and automatically interconnecting the schematic design elements. The PCB is then physically designed based on the interconnected HDL and schematic design elements. The method may further comprise creating a schematic version from the interconnected HDL design elements, and creating a HDL version from the interconnected schematic design elements. The inventive method also may simulate the schematic version of the HDL design elements, and simulate the HDL version of the schematic design elements.

Abstract: A single ASIC memory controller has full interconnectivity between various modes on the ASIC: input controller, memory controller, and output controller. The single ASIC includes an input controller section, a memory controller section, and an output controller section. The ASIC architecture is designed to allow any of the sections to be bypassed. Using the bypass mechanism, the ASIC can be combined with other like ASICs to increase system performance and capabilities without the need for ASIC redesign. The ASIC design can be used in memory subsystems that are scalable depending on user requirements.

Abstract: A system and method is provided for assigning job numbers to fetch requests that are sent to a memory system in order and completed by the memory system out-of-order. A unique set of job numbers represent addresses in a memory fetch list. A valid register maintains status bits associated with the set of job numbers that identify whether a job number is assigned or available. Bits in the valid register are set when an associated job number is assigned and reset when an associated job number is completed. On assignment, a priority encoder selects any lowest available job number based upon the status of the bits in the valid register. In the preferred embodiment, the lowest available job number is selected.

Abstract: A method and a switching system for connecting multiple requestors to multiple memory units simultaneously. This is accomplished by a switching system that employs multiplexing logic, control logic, multiple data input and output ports and a unique system interconnection topology. Independent data input ports comprised of multiplexing logic controlled by a control logic, simultaneously channel multiple fetch and store commands from the requestors to the memory units. Similarly, independent data output ports comprised of a second multiplexing logic controlled by a second control logic, simultaneously channels multiple return signals from the memory units to the requestors. The switching system of the present invention incorporates the unique system interconnection topology concept of feed-through boards and modular backplane boards.

Abstract: Modular expansion of a backplane is achieved by means of a modular backplane circuit board that plugs into the backplane side of a backplane parallel to that backplane. The backplane board provides a parallel backplane path between boards on the computer system. When unit boards are added to the foreplane side which require additional electrical paths for connection purposes, a modular backplane board may be added to the backplane side of the backplane to provide such path. In the preferred embodiment a gate array is added to the backplane board to provide management functions in handling the electrical connections on the backplane board.