Patents by Inventor Anthony P. Valpiani

Anthony P. Valpiani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200218314
    Abstract: Particular embodiments described herein provide for an electronic device that could include a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a display portion and a keyboard portion that includes a cradle dock to allow the display portion to be removably connected to the keyboard portion in a first configuration, where a viewing angle of the display portion can be adjusted.
    Type: Application
    Filed: November 14, 2019
    Publication date: July 9, 2020
    Inventors: Michael Hui, Russell S. Aoki, Anthony P. Valpiani, Nicolas A. Kurczewski
  • Patent number: 10680367
    Abstract: Embodiments of the disclosure are directed to a linear edge connector assembly for connecting to a substrate diving board of a mother board. The linear edge connector assembly can include an electrical interface to electrically connect the contacts on the diving board to one or more conducts of a cable bundle. The linear edge connector assembly can also include a retaining force mechanism. The retaining force mechanism can include a torsional spring, a spring loaded hooking mechanism, or a spring loaded cam and lever. In some embodiments, the linear edge connector can include a notch to receive a latch connected to a bolster plate on the mother board.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Feifei Cheng, Kuang C. Liu, Michael Garcia, Eric W. Buddrius, Kevin J. Ceurter, Anthony P. Valpiani, Jonathon Robert Carstens
  • Patent number: 10481643
    Abstract: Particular embodiments described herein provide for an electronic device that could include a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a display portion and a keyboard portion that includes a cradle dock to allow the display portion to be removably connected to the keyboard portion in a first configuration, where a viewing angle of the display portion can be adjusted.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Michael Hui, Russell S. Aoki, Anthony P. Valpiani, Nicolas A. Kurczewski
  • Publication number: 20180210506
    Abstract: Particular embodiments described herein provide for an electronic device that could include a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a display portion and a keyboard portion that includes a cradle dock to allow the display portion to be removably connected to the keyboard portion in a first configuration, where a viewing angle of the display portion can be adjusted.
    Type: Application
    Filed: August 29, 2017
    Publication date: July 26, 2018
    Applicant: Intel Corporation
    Inventors: Michael Hui, Russell S. Aoki, Anthony P. Valpiani, Nicolas A. Kurczewski
  • Patent number: 9991223
    Abstract: Embodiments of the present disclosure describe package alignment frames for a local reflow process to attach a semiconductor package to an interposer. The frame may comprise a two frame system. The interposer may be on a mounting table or on a circuit board. The frame may include a body with a rectangular opening dimensioned to receive a semiconductor package to be coupled to the interposer. The frame may be to align a ball grid array of the semiconductor package with pads of the interposer. A second frame may be to receive the first frame and may be to align a ball grid array of the interposer with pads of the circuit board. A single frame may be used to couple a semiconductor package to an interposer and to couple the interposer to a circuit board. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Russell S. Aoki, Michael R. Hui, Jonathon R. Carstens, Michael S. Brazel, Daniel P. Carter, Thomas A. Boyd, Shelby A. Ferguson, Rashelle Yee, Joseph J. Jasniewski, Harvey R. Kofstad, Anthony P. Valpiani
  • Publication number: 20170288330
    Abstract: Embodiments of the disclosure are directed to a linear edge connector assembly for connecting to a substrate diving board of a mother board. The linear edge connector assembly can include an electrical interface to electrically connect the contacts on the diving board to one or more conducts of a cable bundle. The linear edge connector assembly can also include a retaining force mechanism. The retaining force mechanism can include a torsional spring, a spring loaded hooking mechanism, or a spring loaded cam and lever. In some embodiments, the linear edge connector can include a notch to receive a latch connected to a bolster plate on the mother board.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 5, 2017
    Applicant: Intel Corporation
    Inventors: Feifei Cheng, Kuang C. Liu, Michael Garcia, Eric W. Buddrius, Kevin J. Ceurter, Anthony P. Valpiani, Jonathon Robert Carstens
  • Patent number: 9766661
    Abstract: Particular embodiments described herein provide for an electronic device that could include a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a display portion and a keyboard portion that includes a cradle dock to allow the display portion to be removably connected to the keyboard portion in a first configuration, where a viewing angle of the display portion can be adjusted.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Michael Hui, Russell Aoki, Anthony P. Valpiani, Nicolas A. Kurczewski
  • Publication number: 20170179067
    Abstract: Embodiments of the present disclosure describe package alignment frames for a local reflow process to attach a semiconductor package to an interposer. The frame may comprise a two frame system. The interposer may be on a mounting table or on a circuit board. The frame may include a body with a rectangular opening dimensioned to receive a semiconductor package to be coupled to the interposer. The frame may be to align a ball grid array of the semiconductor package with pads of the interposer. A second frame may be to receive the first frame and may be to align a ball grid array of the interposer with pads of the circuit board. A single frame may be used to couple a semiconductor package to an interposer and to couple the interposer to a circuit board. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Inventors: RUSSELL S. AOKI, MICHAEL R. HUI, JONATHON R. CARSTENS, MICHAEL S. BRAZEL, DANIEL P. CARTER, THOMAS A. BOYD, SHELBY A. FERGUSON, RASHELLE YEE, JOSEPH J. JASNIEWSKI, HARVEY R. KOFSTAD, ANTHONY P. VALPIANI
  • Publication number: 20170178994
    Abstract: Disclosed herein are integrated circuit (IC) package support structures, and related systems, devices, and methods. In some embodiments, an IC package support structure may include a first heater trace, and a second heater trace, wherein the second heater trace is not conductively coupled to the first heater trace in the IC package support structure.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: Michael Hui, Rashelle Yee, Jonathan Thibado, Daniel P. Carter, Shelby Ferguson, Anthony P. Valpiani, Russell S. Aoki, Jonathon Robert Carstens, Joseph J. Jasniewski, Harvey R. Kofstad, Michael Brazel, Tracy Clack, Viktor Vogman, Penny Woodcock, Kevin J. Ceurter, Hongfei Yan
  • Publication number: 20170179066
    Abstract: Reflow Grid Array technology may be implemented on an interposer device, where the interposer is placed between a motherboard and a BGA package. The interposer may provide a controlled heat source to reflow solder between the interposer and the BGA package. A technical problem faced by an interposer using RGA technology is solder cleaning and removal when removing a BGA package. Technical solutions described herein provide processes and equipment for bulk solder removal from a BGA package that can be executed in the field.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Inventors: Russell S. Aoki, John W. Jaeger, Michael S. Brazel, Daniel P. Carter, Anthony P. Valpiani, Michael R. Hui, Rashelle Yee, Joseph J. Jasniewski, Shelby A. Ferguson, Thomas A. Boyd, Jonathan W. Thibado, Penny K. Woodcock, Rachel G. Taylor, Laura S. Mortimer
  • Patent number: 9258914
    Abstract: In one embodiment chassis for an electronic device comprises a first section and a second section and an assembly to connect a first section of the chassis to a second section of the chassis, comprising a hinge assembly to be coupled between the first section of the chassis and the second section of the chassis to allow rotation of the second section of the chassis with respect to the first section of the chassis, and a translation assembly to be coupled to the hinge assembly of the chassis for the electronic device to allow translation of the second section of the chassis with respect to the first section of the chassis, wherein rotation of the hinge assembly activates the translation assembly. Other embodiments may be described.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: February 9, 2016
    Assignee: Intel Corporation
    Inventors: Alanna M. Koser, Robert R. Atkinson, Jr., Ralph V. Miele, Anthony P. Valpiani
  • Patent number: 9244487
    Abstract: A land-grid array die package socket is configured for low- or zero insertion-force assembly with a land-grid array die package. For zero insertion-force assembly, a motion plate applies a force on a land-grid array contact that causes a contact tip to move into protective cover while the die package is inserted into the socket. After zero insertion-force assembly, the motion plate applies a force on the land-grid array contact that causes the contact tip to deflect in a positive-Z direction until a useful contact is made at the contact tip with a land-grid array pad.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: January 26, 2016
    Assignee: Intel Corporation
    Inventors: Russell S. Aoki, Anthony P. Valpiani, Barry T. Dale, Chia-Pin Chiu
  • Publication number: 20150305185
    Abstract: In one embodiment chassis for an electronic device comprises a first section and a second section and an assembly to connect a first section of the chassis to a second section of the chassis, comprising a hinge assembly to be coupled between the first section of the chassis and the second section of the chassis to allow rotation of the second section of the chassis with respect to the first section of the chassis, and a translation assembly to be coupled to the hinge assembly of the chassis for the electronic device to allow translation of the second section of the chassis with respect to the first section of the chassis, wherein rotation of the hinge assembly activates the translation assembly. Other embodiments may be described.
    Type: Application
    Filed: July 30, 2013
    Publication date: October 22, 2015
    Inventors: Alanna M. KOSER, Robert R. ATKINSON, JR., Ralph V. MIELE, Anthony P. VALPIANI
  • Publication number: 20150036273
    Abstract: Particular embodiments described herein provide for an electronic device that could include a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a display portion and a keyboard portion that includes a cradle dock to allow the display portion to be removably connected to the keyboard portion in a first configuration, where a viewing angle of the display portion can be adjusted.
    Type: Application
    Filed: July 30, 2013
    Publication date: February 5, 2015
    Inventors: Michael Hui, Russell Aoki, Anthony P. Valpiani, Nicolas A. Kurczewski
  • Publication number: 20140162473
    Abstract: A mobile device assembly comprising a land grid array (LGA) socket configured to couple with a board of a mobile device. The LGA socket may be configured to couple with a component of the mobile device. A mobile independent loading mechanism (ILM) may at least partially overlap the component and couple with the board of the mobile device via one or more fasteners. By coupling with the board of the mobile device, the mobile ILM may therefore apply pressure to the component, securely holding the component to the LGA socket.
    Type: Application
    Filed: December 11, 2012
    Publication date: June 12, 2014
    Inventors: Russell S. Aoki, Anthony P. Valpiani
  • Publication number: 20140082915
    Abstract: A land-grid array die package socket is configured for low- or zero insertion-force assembly with a land-grid array die package. For zero insertion-force assembly, a motion plate applies a force on a land-grid array contact that causes a contact tip to move into protective cover while the die package is inserted into the socket. After zero insertion-force assembly, the motion plate applies a force on the land-grid array contact that causes the contact tip to deflect in a positive-Z direction until a useful contact is made at the contact tip with a land-grid array pad.
    Type: Application
    Filed: November 26, 2013
    Publication date: March 27, 2014
    Inventors: Russell S. Aoki, Anthony P. Valpiani, Barry T. Dale, Chia-Pin Chiu
  • Patent number: 8622764
    Abstract: A land-grid array die package socket is configured for low- or zero insertion-force assembly with a land-grid array die package. For zero insertion-force assembly, a motion plate applies a force on a land-grid array contact that causes a contact tip to move into protective cover while the die package is inserted into the socket. After zero insertion-force assembly, the motion plate applies a force on the land-grid array contact that causes the contact tip to deflect in a positive-Z direction until a useful contact is made at the contact tip with a land-grid array pad.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: January 7, 2014
    Assignee: Intel Corporation
    Inventors: Russell S. Aoki, Anthony P. Valpiani, Barry T. Dale, Chia-Pin Chiu
  • Publication number: 20120200993
    Abstract: A land-grid array die package socket is configured for low- or zero insertion-force assembly with a land-grid array die package. For zero insertion-force assembly, a motion plate applies a force on a land-grid array contact that causes a contact tip to move into protective cover while the die package is inserted into the socket. After zero insertion-force assembly, the motion plate applies a force on the land-grid array contact that causes the contact tip to deflect in a positive-Z direction until a useful contact is made at the contact tip with a land-grid array pad.
    Type: Application
    Filed: February 9, 2011
    Publication date: August 9, 2012
    Inventors: Russell S. Aoki, Anthony P. Valpiani, Barry T. Dale, Chia-Pin Chiu
  • Patent number: 6854693
    Abstract: A tie wrap assembly comprises a tie wrap, for retaining a cable assembly, and a tie wrap base, for connecting the cable assembly to the chassis. The tie wrap includes a shaped engagement member for fittably coupling to an orifice within the tie wrap base. The tie wrap base is flexible, allowing the engagement member to be repeatedly inserted into and removed from the tie wrap base, as well as being fit through a hole in the chassis. One or more tie wrap bases are disposed at pre-arranged locations along the chassis. The tie wrap assembly allows cabling to be consistently routed along the pre-arranged locations, facilitating the consistent placement of cables in a mass production environment.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: February 15, 2005
    Assignee: Intel Corporation
    Inventors: Joe A. Harrison, Anthony P. Valpiani
  • Publication number: 20040104314
    Abstract: A tie wrap assembly comprises a tie wrap, for retaining a cable assembly, and a tie wrap base, for connecting the cable assembly to the chassis. The tie wrap includes a shaped engagement member for fittably coupling to an orifice within the tie wrap base. The tie wrap base is flexible, allowing the engagement member to be repeatedly inserted into and removed from the tie wrap base, as well as being fit through a hole in the chassis. One or more tie wrap bases are disposed at pre-arranged locations along the chassis. The tie wrap assembly allows cabling to be consistently routed along the pre-arranged locations, facilitating the consistent placement of cables in a mass production environment.
    Type: Application
    Filed: December 3, 2002
    Publication date: June 3, 2004
    Inventors: Joe A. Harrison, Anthony P. Valpiani