Abstract: A clock circuit is initiated by an external trigger pulse. Timing measurements commence at a first rate, and after a first delay (t.sub.1) which is sufficient to allow an oscillator of the clock circuit to stabilize. After a second delay (t.sub.1) the clock circuit operates at a second rate which is half the first rate. The clock circuit then represents the time from reception of the external trigger pulse. The first and second delays are derived by charging a capacitor at a constant rate and comparing the voltage level developed across it with respective reference voltages (V.sub.1, V.sub.2) in comparators.In general, the second rate may be 1/r+1 times the first rate, where r is the ratio of the first delay to the second delay.