Abstract: Various embodiments of the present technology may provide methods and apparatus for a time-to-digital converter. The time-to-digital converter may include a state machine that increments/decrements according to an input signal and a count value. The time-to-digital converter may further include a register to store the count value according to the input signal.

Abstract: Various embodiments of the present technology may provide methods and apparatus for a time-to-digital converter. The time-to-digital converter may include a state machine that increments/decrements according to an input signal and a count value. The time-to-digital converter may further include a register to store the count value according to the input signal.

Abstract: A system is provided that is configured to encode an image in accordance with a variable resolution image format. The variable resolution image format allows the specification of a number of windows in terms of their location and resolution. The image can be decomposed into a minimum number of square superpixels such that all specified windows are at the assigned resolution or better. By encoding one image where only critical portions are at the high resolution while less critical portions are at intermediate or lower resolutions, the number of bits that need to be transmitted from the system to a remote host subsystem can be dramatically reduced.

Abstract: Various embodiments of the present technology may provide methods and apparatus for a time-to-digital converter. The time-to-digital converter may include a state machine that increments/decrements according to an input signal and a count value. The time-to-digital converter may further include a register to store the count value according to the input signal.

Abstract: Various embodiments of the present technology may comprise a method and apparatus for in-place fast Fourier transform (FFT). According to various embodiments, the apparatus comprises a RAM, having a single address space, divided into a plurality of sub-memory spaces, where the number of sub-memory spaces is a function of a length of the FFT such that the two inputs are always from different sub-memories, as are the two outputs. According to various embodiments, the apparatus may further comprise a division circuit configured to perform a “bitwise” division operation in order to convert addresses from the aforementioned single address space to the particular sub-memories and addresses within them. According to various embodiments, the apparatus may further comprise a butterfly processor capable of performing a butterfly operation.

Abstract: Various embodiments of the present technology may comprise a method and apparatus for in-place fast Fourier transform (FFT). According to various embodiments, the apparatus comprises a RAM, having a single address space, divided into a plurality of sub-memory spaces, where the number of sub-memory spaces is a function of a length of the FFT such that the two inputs are always from different sub-memories, as are the two outputs. According to various embodiments, the apparatus may further comprise a division circuit configured to perform a “bitwise” division operation in order to convert addresses from the aforementioned single address space to the particular sub-memories and addresses within them. According to various embodiments, the apparatus may further comprise a butterfly processor capable of performing a butterfly operation.

Abstract: A motion estimator includes a shape, address and vector generator to produce control signals according to a selected size and shape of a search area comprising scan lines. A variable delay reads reference image data of a frame in which a matching macroblock is sought from a store under control of a variable delay control signal from the signal generator to align a current serial input stream of a current scan line with a serial input stream of an immediately preceding scan line. The aligned reference image pixel data is matched against pixel data of a current macroblock using a vector from the signal generator to produce a score representing a quality of the match. A best score together with the corresponding best vector is recorded and the best vector output.

Abstract: A logic circuit is configured to calculate a sliding sum of absolute differences of a plurality of numbers from a plurality of members respectively selected successively from all members of a sequence of numbers. The logic circuit reduces an amount of logic that is required to perform the sum of absolute differences, and thereby saves resources and latency.

Abstract: A recursive filter system and method is provided. A weighted value of luminance and chrominance of a stored picture element is generated by summing weighted values of luminance and chrominance of a picture element and neighboring picture elements. A first proportional parameter for the stored picture element is generated with a sum of differences between the luminance and chrominance of the stored picture element and surrounding picture elements. A weighted picture element is generated from a proportion of the stored picture element and a complimentary proportion of the weighted value. Picture elements of the next image and a second proportional parameter are inputted. A filtered image is generated by combining a proportion of each input picture element of the next image with a complementary proportion of the weighted stored picture element of the first image. The filtered image is stored for corresponding combination with a succeeding image.

Abstract: Encoded symbols of a concatenated convolutional-encoded and block encoded signal are presented to a conventional first stage of a concatenated decoder, comprising in sequence a soft metric generator, a Viterbi decoder, a first de-interleaver and a first block decoder such as a Reed-Solomon decoder. The encoded symbols are also presented to a delay chain to produce progressively delayed encoded symbols. Where an output block of the conventional decoder is indicated as being a valid codeword by the first block decoder, the bytes in this block are marked as being correct. These bytes that are known to be correct are then used after interleaving and serialization as known bits input to a second stage of the decoder process operating on the delayed encoded symbols and incorporating a modified soft metric generator constrained by the known bits. This process can be extended to further iterations as required.

Abstract: A logic circuit is configured to calculate a sliding sum of absolute differences of a plurality of numbers from a plurality of members respectively selected successively from all members of a sequence of numbers.

Abstract: Motion compensation means for a time recursive filter includes a block motion estimation module (12) having an input video signal (1) and a input delayed output signal (6) of the time recursive filter. The block motion estimation module outputs block motion vectors (13) to at least one block splitting stage (14, 16, 18) which together with the input video signal (1) and the delayed output signal (6) of the time recursive filter is arranged to produce at least sub-block motion vectors (15, 17, 19) for input into image reconstruction means (9) to produce a motion-compensated image (11).

Abstract: A motion estimator 50 for image processing finds a motion vector from a search area in a reference picture to a source macroblock in a source picture by finding a maximum of a 2-dimensional normalised cross-correlation surface between the source macroblock and a portion of the reference search area using a transform domain.

Abstract: A method and apparatus detects the presence of a watermark in digital data. The digital data may represent picture or sound information and maybe in the form of a broadcast television signal or a signal that has been recorded on a recording medium such as a compact disc. The watermark includes coefficients which have been subject to an inverse local orthogonal transform before being embedded in the input data. In order to detect the presence of the watermark, the input watermarked data is first forward transformed and subtracted from the watermark coefficients so as to derive the data coefficients. The data coefficients are squared and formed into a local average to obtain a measure of the power in the local average. The watermark coefficients are divided by the local average so as to scale them and the scaled watermark coefficients are cross-correlated with the input data to detect whether the watermark is present.

Abstract: A concatenated convolutional encoded and block encoded signal is decoded conventionally using a first Viterbi decoder (22), a de-interleaver (23) and a block decoder. Blocks correctly decoded by the block decoder are identified by the block decoder and marked in an output signal from the block decoder. The marked decoded signal is interleaved (26) to form an interleaved marked decoded signal. A delayed version of the encoded signal (21′) is decoded with a second Viterbi decoder (32), using the known bits from the marked decoded signal. That is, states of the encoder with which the encoded signal was encoded which are inconsistent with known bits from known blocks are discounted in the second Viterbi decoding, as are any transitions passing through such a state. This may be visualised as constraining a Viterbi trellis in the vicinity of the known bits. Output from the second Viterbi decoder may be de-interleaved (33) and block decoded (34) to form a decoded output.

Abstract: A convolutional encoded signal, having at least one predetermined bit at a predetermined bit location in the signal, is decoded, taking into account the at least one predetermined bit. As in a known Viterbi decoder, error coefficients are determined, representative of differences between successively received encoded symbols of the encoded signal, representative of transitions of the state of an encoder with which the signal was encoded, and predetermined permitted transitions from the said states. Sums of error coefficients corresponding to successions of transitions are determined to find a succession of transitions having a least sum, representative of a least error decoded signal. However, states which are inconsistent with the predetermined bit at the predetermined bit location are effectively discounted, as are any transitions passing through such a state. This may be visualised as constraining a Viterbi trellis in the vicinity of the at least one predetermined bit.

Abstract: An apparatus for producing a product code having a first dimension systematic block code of length nx elements and a second dimension systematic block code of length ny elements has a first dimension encoder 12 for receiving a data element stream 11 to produce the first dimension block code having kx data elements and nx−kx parity elements, the parity elements being derived from the data elements. The first dimension encoder is arranged to produce ky first dimension code vectors where ky is the data element length of the second dimension systematic block code. The second dimension encoder 14-16 is representative of nx encoders. The second dimension encoder receives the first dimension code vectors as they are produced and derives (nxny-nxky) parity elements for the second dimension systematic block code.