Abstract: The present invention is a method of reducing latency in transmitting frames of data in a shared access media environment whereby the preamble of the next frame to be transmitted is transmitted while the data portion of the next frame to be transmitted is being retrieved. In another aspect, the early transmission of the preamble of the next frame is started no later than the time it normally takes to fetch and prepare the next frame for transmission less the time it takes to transmit the preamble.

Abstract: A circuit (10) for producing a single output data (DOUT) stream and a corresponding single clock signal (CLKOUT). This circuit comprises an input for receiving a single input data stream (DIN), where the input data stream has data words at a first frequency. This circuit further includes a plurality of clock inputs for receiving a plurality of corresponding clock signals (CLK0, CLK1), where each of the plurality of corresponding clock signals is synchronized to a corresponding plurality of the data words. This circuit still further includes an input for receiving a fast clock signal (CLKF), where the fast clock signal has a fast frequency greater than the first frequency. The circuit also includes various circuitry. This circuitry includes circuitry for sampling (L20, L21) the input data stream at the fast frequency, circuitry for outputting (M, LM) the sampled data as the single output data stream, and circuitry for outputting (CG) the single clock cycle in response to the fast clock signal.

Abstract: A system (20) for communicating request information from a first circuit (state machine A) operable according to a first clock domain (CLKA) to a second circuit (state machine B) operable according to a second clock domain (CLKB). In the system, the first clock domain differs from the second clock domain. The system comprises a flag circuit (F2) for storing a flag having a changeable state. The flag circuit comprises an input for receiving a toggle control signal (TOGGLE) and the state of the flag changes in response to assertion of the toggle control signal, where the first circuit is operable to assert the toggle signal to communicate the request information to the second circuit. The system further comprises a synchronizing circuit (SCD) having an input coupled to an output of the flag circuit and for receiving the state of the flag. The system further comprises a detection circuit (ED) having an input coupled to an output of the synchronizing circuit.

Abstract: The present invention provides for a statistics Cyclic Redundancy Check (CRC) (108) wherein the statistics CRC (108) is representative of the values contained within a statistics RAM (110). The statistics CRC (108) is then used to reduce test vectors by allowing the validity of the statistics to be determined by reading this signature instead of reading all the individual statistics. The signature is regenerated for each complete pass of the statistics, and the contents of this register are only updated when the pass is complete.

Abstract: A circuit (43) generates one or more signals to be delayed by a corresponding time intervals. Tapped delay lines (40) are coupled to the signals, each tapped delay line including a plurality of delay elements (42) and having a plurality of exit points (E) through which said signal may propagate. A test circuit (20) determines a delay associated with a delay element in the circuit and selects one of said exit points of each of said tapped delay lines based on said delay.