Patents by Inventor Anthony Saporito

Anthony Saporito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11403222
    Abstract: Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: August 2, 2022
    Assignee: International Business Machines Corporation
    Inventors: Christian Jacobi, Ulrich Mayer, Martin Recktenwald, Anthony Saporito, Aaron Tsai
  • Patent number: 11366759
    Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes identifying a storage operand request as restrained, where the identifying includes obtaining, by a processing unit, an access intent instruction indicating an access intent associated with an operand of a next sequential instruction. The access intent indicates usage of the storage operand request is restrained. Further, the method includes determining whether a storage operand request is to a common storage location shared by multiple processing units of a computing environment and is identified restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: June 21, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce C. Giamei, Christian Jacobi, Daniel V. Rosa, Anthony Saporito, Donald W. Schmidt, Chung-Lung K. Shum
  • Publication number: 20220188412
    Abstract: Aspects include circuitry that includes a first global generation counter (GGC) that is increased upon decoding of a branch instruction and a second GGC that is increased upon a completion of the branch instruction. Upon a triggered rollback, the first GGC is reset. The circuitry also includes a generation tag memory associated with a register that receives loads during a side-channel attacks which is set to the first GGC upon a first load, and a determination unit to determine, for a second load from an address depending on the register of the first load, a generation tag value associated with the register of the second load as a function of the first GGC, the second GGC, and the generation tag value associated with the register of the first load. A wait queue is configured to block the second load, if the generation tag is larger than the second GGC.
    Type: Application
    Filed: December 15, 2020
    Publication date: June 16, 2022
    Inventors: Christian Borntraeger, Jonathan D. Bradbury, Martin Recktenwald, Anthony Saporito
  • Patent number: 11256511
    Abstract: A method of performing instruction scheduling during execution in a processor includes receiving, at an execution unit of the processor, an initial assignment of an assigned execution resource among two or more execution resources to execute an operation. An instruction includes two or more operations. Based on determining that the assigned execution resource is not available, the method also includes determining, at the execution unit, whether another execution resource among the two or more execution resources is available to execute the operation. Based on determining that the other execution resource is available, the method further includes executing the operation with the other execution resource.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: February 22, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cedric Lichtenau, Stefan Payer, Kerstin Claudia Schelm, Anthony Saporito, Gregory William Alexander
  • Patent number: 11243774
    Abstract: Methods, systems and computer program products for dynamically selecting an OSC hazard avoidance mechanism are provided. Aspects include receiving a load instruction that is associated with an operand store compare (OSC) prediction. The OSC prediction is stored in an entry of an OSC history table (OHT) and includes a multiple dependencies indicator (MDI). Responsive to determining the MDI is in a first state, aspects include applying a first OSC hazard avoidance mechanism in relation to the load instruction. Responsive to determining that the load instruction is dependent on more than one store instruction, aspects include placing the MDI in a second state. The MDI being in the second state provides an indication to apply a second OSC hazard avoidance mechanism in relation to the load instruction.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: February 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James Raymond Cuffney, Adam Collura, James Bonanno, Edward Malley, Anthony Saporito, Jang-Soo Lee, Michael Cadigan, Jr., Jonathan Hsieh
  • Publication number: 20220012159
    Abstract: A method for collaborative logic designing and debugging of a circuit includes initiating, via a session manager, a hardware debug session that includes a plurality of instances of client applications that can access one or more source-codes associated with a logic design of the circuit, the plurality of instances of client applications configured to replicate an execution state of the logic design. The method also includes analyzing, using an instance of a first client application from the plurality of instances of client applications, a defect in the logic design based on the execution state of the logic design. The method also includes editing, using an instance of a second client application from the plurality of instances of client applications, the one or more source-codes, to repair the defect in the logic design.
    Type: Application
    Filed: July 7, 2020
    Publication date: January 13, 2022
    Inventors: Arun Joseph, Wolfgang Roesner, Anthony Saporito, Matthias Klein, SAMPATH GOUD BADDAM, Shashidhar Reddy
  • Patent number: 11182165
    Abstract: A system includes a branch predictor and a processing circuit configured to perform a plurality of operations including storing a skip-over offset value in the branch predictor. The skip-over offset value defines a number of search addresses of the branch predictor to be skipped. The operations further include searching the branch predictor for a branch prediction. Responsive to finding the branch prediction, the searching of the branch predictor is re-indexed based on the skip-over offset value associated with the branch prediction.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: November 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James Bonanno, Daniel Lipetz, Brian Robert Prasky, Anthony Saporito, Adam Collura, Steven J. Hnatko
  • Patent number: 11182293
    Abstract: A computer implemented method to operate different processor cache levels of a cache hierarchy for a processor with pipelined execution is suggested. The cache hierarchy comprises at least a lower hierarchy level entity and a higher hierarchy level entity. The method comprises: sending a fetch request to the cache hierarchy; detecting a miss event from a lower hierarchy level entity; sending a fetch request to a higher hierarchy level entity; and scheduling at least one write pass.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Simon H. Friedmann, Christian Jacobi, Markus Kaltenbach, Ulrich Mayer, Anthony Saporito
  • Patent number: 11175923
    Abstract: A computer-implemented method for marking load and store instruction overlap in a processor pipeline is described. The method includes detecting a load instruction following a store instruction in an instruction stream. The load instruction and the store instruction include instruction text. The instruction text includes operand address information. The method includes comparing operand address information of the store instruction with operand address information of the load instruction to determine whether there is a memory image overlap in an issue queue between the operand address information of the store instruction and the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to determining that there is a memory image overlap.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregory W. Alexander, James J. Bonanno, Adam B. Collura, Bruce C. Giamei, Christian Jacobi, Jang-Soo Lee, Edward T. Malley, Lawrence J. Powell, Jr., Anthony Saporito
  • Patent number: 11169922
    Abstract: A computer implemented method for saving cache access power is suggested. The cache is provided with a set predictor logic for providing a generated set selection for selecting a set in the cache, and with a set predictor cache for pre-caching generated set indices of the cache. The method comprises further: receiving a part of a requested memory address; checking, in the set predictor cache, whether the requested memory address is already generated; in the case, that the requested memory address has already been generated: securing that the set predictor cache is switched off; issuing the pre-cached generated set index towards the cache; and securing that only that part of the cache is switched on that is associated with the pre-cached generated set index.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: November 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Christian Jacobi, Markus Kaltenbach, Ulrich Mayer, Johannes C. Reichart, Anthony Saporito, Siegmund Schlechter
  • Patent number: 11163573
    Abstract: A system includes a hierarchical metadata predictor and a processing circuit. The hierarchical metadata predictor includes a first-level metadata predictor and a second-level metadata predictor. The processing circuit is configured to perform a plurality of operations including storing new or updated metadata into the first-level metadata predictor and searching the first-level metadata predictor for a metadata prediction. Responsive to finding the metadata prediction in the first-level metadata predictor, the metadata prediction is output corresponding to an entry of the first-level metadata predictor that is a hit. One or more entries of the first-level metadata predictor that are non-hits are periodically written to the second-level metadata predictor. The first-level metadata predictor is updated based on locating the metadata prediction in the second-level metadata predictor.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: November 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James Bonanno, Varnika Atmakuri, Adam Collura, Brian Robert Prasky, Anthony Saporito, Suman Amugothu
  • Patent number: 11113055
    Abstract: A computer implemented method for marking a store instruction overlap in a processor pipeline is provided. A non-limiting example of the method includes detecting a second store instruction subsequent to a first store instruction in an instruction stream, in which there is a match between the operand address information of the first store instruction and a load instruction. The operand address information of the first store instruction is compared with the operand address information of the second store instruction to determine whether there is match. In the event of a match, the second store instruction is delayed in the processor pipeline in response to determining that there is a memory image overlap between the operand address information of the second store instruction and the first store instruction.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: September 7, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edward Malley, Jang-Soo Lee, Anthony Saporito, Chung-Lung K. Shum, Gregory William Alexander
  • Patent number: 11080052
    Abstract: Effectiveness of prefetch instructions is determined. A prefetch instruction is executed to request that data be fetched into a cache of the computing environment. The effectiveness of the prefetch instruction is determined. This includes updating, based on executing the prefetch instruction, a cache directory of the cache. The updating includes, in the cache directory, effectiveness data relating to the data. The effectiveness data includes whether the data was installed in the cache based on the prefetch instruction. Additionally, the determining the effectiveness includes obtaining at least a portion of the effectiveness data from the cache directory, and using the at least a portion of effectiveness data to determine the effectiveness of the prefetch instruction.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 3, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel
  • Publication number: 20210232502
    Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.
    Type: Application
    Filed: April 9, 2021
    Publication date: July 29, 2021
    Inventors: Christian Zoellin, Christian Jacobi, Chung-Lung K. Shum, Martin Recktenwald, Anthony Saporito, Aaron Tsai
  • Patent number: 11010298
    Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: May 18, 2021
    Assignee: International Business Machines Corporation
    Inventors: Christian Zoellin, Christian Jacobi, Chung-Lung K. Shum, Martin Recktenwald, Anthony Saporito, Aaron Tsai
  • Patent number: 11010066
    Abstract: A guarded storage facility sets up a boundary indicating a range of addresses to be guarded or protected. When a program attempts to access an address in a guarded section defined by the boundary, a guarded storage event occurs. Use of this facility facilitates performance of certain tasks within a computing environment, including storage reclamation.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 18, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Marcel Mitran, Volodymyr Paprotski, Anthony Saporito, Timothy J. Slegel
  • Patent number: 11010168
    Abstract: A method, system, and computer program product are provided for prioritizing prefetch instructions. The method includes a processor issuing a prefetch instruction and fetching elements from a cache that can include a memory or a higher level cache. The processor stores the elements in temporary storage and monitors for accesses by an instruction. The processor stores a record representing the prefetch instruction. The processor updates the record with an indicator and issues a new prefetch instruction by comparing the new prefetch instruction to the record, based on the new prefetch instruction matching the prefetch instruction, assigning the indicator to the new prefetch instruction as a priority value, based on the new prefetch instruction not matching the prefetch instruction, assigning a default value to the new prefetch instruction as the priority value, and determining whether to execute the new prefetch instruction, based on the priority value of the new prefetch instruction.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: May 18, 2021
    Assignee: International Business Machines Corporation
    Inventors: Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum
  • Patent number: 11003452
    Abstract: A method, system, and computer program product are provided for prioritizing prefetch instructions. The method includes a processor issuing a prefetch instruction and fetching elements from a cache that can include a memory or a higher level cache. The processor stores the elements in temporary storage and monitors for accesses by an instruction. The processor stores a record representing the prefetch instruction. The processor updates the record with an indicator and issues a new prefetch instruction by comparing the new prefetch instruction to the record, based on the new prefetch instruction matching the prefetch instruction, assigning the indicator to the new prefetch instruction as a priority value, based on the new prefetch instruction not matching the prefetch instruction, assigning a default value to the new prefetch instruction as the priority value, and determining whether to execute the new prefetch instruction, based on the priority value of the new prefetch instruction.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: May 11, 2021
    Assignee: International Business Machines Corporation
    Inventors: Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum
  • Patent number: 10997079
    Abstract: A computer implemented method for saving cache access power is suggested. The cache is provided with a set predictor logic for providing a generated set selection for selecting a set in the cache, and with a set predictor cache for pre-caching generated set indices of the cache. The method comprises further: receiving a part of a requested memory address; checking, in the set predictor cache, whether the requested memory address is already generated; in the case, that the requested memory address has already been generated: securing that the set predictor cache is switched off; issuing the pre-cached generated set index towards the cache; and securing that only that part of the cache is switched on that is associated with the pre-cached generated set index.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: May 4, 2021
    Assignee: International Business Machines Corporation
    Inventors: Christian Jacobi, Markus Kaltenbach, Ulrich Mayer, Johannes C. Reichart, Anthony Saporito, Siegmund Schlechter
  • Publication number: 20210096998
    Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes identifying a storage operand request as restrained, where the identifying includes obtaining, by a processing unit, an access intent instruction indicating an access intent associated with an operand of a next sequential instruction. The access intent indicates usage of the storage operand request is restrained. Further, the method includes determining whether a storage operand request is to a common storage location shared by multiple processing units of a computing environment and is identified restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request.
    Type: Application
    Filed: December 10, 2020
    Publication date: April 1, 2021
    Inventors: Bruce C. GIAMEI, Christian JACOBI, Daniel V. ROSA, Anthony SAPORITO, Donald W. SCHMIDT, Chung-Lung K. SHUM