Abstract: A transistor structure is provided, the structure may be for a high electron mobility transistor (HEMT). The HEMT comprises a channel layer arranged over a substrate, the channel layer may have a top surface. A barrier layer may be arranged over the channel layer. A first opening may be in the barrier layer and extend partially into the channel layer. A first barrier liner may be arranged in the first opening and over the channel layer, the first barrier liner may have a bottom surface. The bottom surface of the first barrier liner may be lower than the top surface of the channel layer.

Abstract: Methods of forming a shear-mode chemical/physical sensor for liquid environment sensing on V-shaped grooves of a [100] crystal orientation Si layer and the resulting devices are provided. Embodiments include forming a set of V-shaped grooves in a [100] Si layer over a substrate; forming an acoustic resonator over and along the V-shaped grooves, the acoustic resonator including a first metal layer, a thin-film piezoelectric layer, and a second metal layer in an IDT pattern or a sheet; and forming at least one functional layer along a slope of the acoustic resonator.

Abstract: One illustrative device disclosed herein includes a semiconductor substrate, a channel that is at least partially defined by at least a portion of the semiconductor substrate, an input fluid reservoir and an output fluid reservoir, wherein the channel is in fluid communication with the input fluid reservoir and the output fluid reservoir. In this example, the device further includes a first radiation source operatively coupled to the substrate, wherein the first radiation source is adapted to generate radiation in a direction toward the channel, and at least one photodiode positioned adjacent the channel.

Abstract: One device disclosed herein includes, among other things, first and second conductive features embedded in a first dielectric layer, a cap layer positioned above the first dielectric layer, a ballistic transport material contacting the first conductive member and positioned above a portion of the first dielectric layer, and first and second contacts contacting the first and second conductive features.

Abstract: One device disclosed herein includes, among other things, first and second conductive features embedded in a first dielectric layer, a cap layer positioned above the first dielectric layer, a ballistic transport material contacting the first conductive member and positioned above a portion of the first dielectric layer, and first and second contacts contacting the first and second conductive features.

Abstract: Methods of forming a shear-mode acoustic wave filter on V-shaped grooves of a [100] crystal orientation Si layer over a substrate and the resulting devices are provided. Embodiments include forming a set of V-shaped grooves in a [100] crystal orientation Si layer over a substrate; and forming a shear-mode acoustic wave filter over the V-shaped grooves, the shear-mode acoustic wave filter including a first metal layer, a thin-film piezoelectric layer, and a second metal layer, wherein the second metal layer is an IDT pattern or a sheet.

Abstract: Methods of forming a shear-mode chemical/physical sensor for liquid environment sensing on V-shaped grooves of a [100] crystal orientation Si layer and the resulting devices are provided. Embodiments include forming a set of V-shaped grooves in a [100] Si layer over a substrate; forming an acoustic resonator over and along the V-shaped grooves, the acoustic resonator including a first metal layer, a thin-film piezoelectric layer, and a second metal layer in an IDT pattern or a sheet; and forming at least one functional layer along a slope of the acoustic resonator.

Abstract: Methods of forming a shear-mode acoustic wave filter on V-shaped grooves of a [100] crystal orientation Si layer over a substrate and the resulting devices are provided. Embodiments include forming a set of V-shaped grooves in a [100] crystal orientation Si layer over a substrate; and forming a shear-mode acoustic wave filter over the V-shaped grooves, the shear-mode acoustic wave filter including a first metal layer, a thin-film piezoelectric layer, and a second metal layer, wherein the second metal layer is an IDT pattern or a sheet.

Abstract: Methods of forming a thin-film piezoelectric acoustic filter, a GaN-channel/buffer Bragg reflector, and a monolithically integrated GaN HEMT PA and CMOS over a [111] crystal orientation Si handle of a SOI wafer and resulting devices are provided. Embodiments include providing a SOI wafer including a [111] crystal orientation Si handle, a BOX layer, and a top Si layer; forming a CMOS device over the top Si layer; and forming a Bragg reflector over the [111] crystal orientation Si handle wafer, the Bragg reflector including a GaN stack with alternating layers of high/low acoustic impedance.

Abstract: Methods of forming a thin-film piezoelectric acoustic filter, a GaN-channel/buffer Bragg reflector, and a monolithically integrated GaN HEMT PA and CMOS over a [111] crystal orientation Si handle of a SOI wafer and resulting devices are provided. Embodiments include providing a SOI wafer including a [111] crystal orientation Si handle, a BOX layer, and a top Si layer; forming a CMOS device over the top Si layer; and forming a Bragg reflector over the [111] crystal orientation Si handle wafer, the Bragg reflector including a GaN stack with alternating layers of high/low acoustic impedance.

Abstract: A magazine device for a firearm is disclosed herein. The magazine device comprises a generally curved elongate casing, a spring-loaded follower frame, a lighting element, and a multiple transparent windows. The follower frame is configured to traverse from a lower end of the casing to an upper end of the casing in predetermined positions according to the depletion of ammunition positioned on each follower frame. The lighting element is housed proximal to a rear section of the follower frame, where the lighting element is configured to illuminate the vicinity of the follower frame. The transparent windows are positioned on the casing, in alignment with the predetermined positions of the follower frame, where the transparent windows are configured to display the level and number of ammunition left in the follower frame after a firing process.

Abstract: Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

Abstract: A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

Abstract: In a method of fabricating a CMOS structure, a bulk device can be formed in a first region in conductive communication with an underlying bulk region of the substrate. A first gate conductor may overlie the first region. An SOI device can be formed which has a source drain conduction path in a SOI layer, i.e., a semiconductor layer that is separated from the bulk region by a buried dielectric region. The crystal orientations of the SOI layer and the bulk region can be different. A first diode can be formed in a second region of the substrate in conductive communication with the bulk region. The first diode may be connected in a reverse-biased orientation to a first gate conductor above the SOI layer, such that a voltage on the gate conductor that exceeds the breakdown voltage can be discharged through the first diode to the bulk region of the substrate. A second diode may be formed in a third region of the substrate in conductive communication with the bulk region.

Abstract: A method for increasing an electrical resistance of a resistor that is within a semiconductor structure. A fraction of a surface layer of the resistor is oxidized with oxygen particles. In an embodiment, the fraction of the surface layer is heated by a beam of particles, such that the semiconductor structure is within a chamber that includes the oxygen particles as gaseous oxygen-comprising molecules. In an embodiment, the semiconductor structure is immersed in a chemical solution which includes the oxygen particles, wherein the oxygen particles includes oxygen-comprising liquid molecules, oxygen ions, or an oxygen-comprising gas dissolved in the chemical solution under pressurization. In an embodiment, the resistor is tested to determine whether the electrical resistance of the resistor after being oxidized with the oxygen particles is within a tolerance of a predetermined target resistance.

Abstract: A method of forming a semiconductor device. A first dielectric layer is deposited on and in direct mechanical contact with the substrate. A first hard mask is deposited on the first dielectric layer. A first and second trench is formed within the first dielectric layer and the first hard mask. The second trench is wider than the first trench. A first conformal liner is deposited over the first hard mask and within the first and second trenches, a portion of which is removed, leaving a remaining portion of the first conformal liner in direct physical contact with the substrate, the first dielectric layer, and the first hard mask, and not on the first hard mask. Copper is deposited over the first conformal liner to overfill fill the first and second trenches and is planarized to remove an excess thereof to form a planar surface of the copper.

Abstract: Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.

Abstract: A system and method to optimize a circuit layout, and more particularly, to a system and method of post layout data preparation to optimize a circuit layout and reduce random and systematic wire and via opens and shorts. The method includes stripping existing vias in a design layout and determining design parameters of the design layout including wiring placement and dimensions. The method further includes optimizing via layout by placing vias away from edges of the wiring and adjacent vias. The invention is also directed to a design structure on which a circuit resides.

Abstract: Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

Abstract: A capacitor structure uses an aperture located within a dielectric layer in turn located over a substrate. A pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalls of the aperture. A pair of capacitor plates is located upon the pair of opposite sidewalls of the aperture and contacting the pair of conductor interconnection layers, but not filling the aperture. A capacitor dielectric layer is located interposed between the pair of capacitor plates and filling the aperture. The pair of capacitor plates may be formed using an anisotropic unmasked etch followed by a masked trim etch. Alternatively, the pair of capacitor plates may be formed using an unmasked anisotropic etch only, when the pair of opposite sidewalls of the aperture is vertical and separated by a second pair of opposite sidewalls that is outward sloped.