Abstract: A system may include a processor configured to: receive ambient data from an environment; calculate an average amplitude of the ambient data as a measure of a noise floor; receive a signal of interest found by the signal exceeding a noise riding threshold, the noise riding floor being an upward offset from the noise floor; calculate a running average for amplitude and frequency of the signal of interest; calculate a running variance for the amplitude and the frequency of the signal of interest; use the running average and the running variance to provide an adjustment to limits for modulation detection; use an offset from the noise riding threshold to provide a signal qualification minimum amplitude; and qualify the signal of interest based at least on the signal qualification minimum amplitude.

Abstract: A system and method for serializing output includes shift registers that sample a deserialized input signal at a relatively slow clock speed. Data latency between the input and output signals is controllable to a higher granularity than the input signal with bit positions corresponding to the high-speed input signal. A predictive learning algorithm receives data latency values from the input signal and corresponding data latency values from the output signal to correct and control output latency, potentially within one high speed clock cycle.

Abstract: A system and method for serializing output includes shift registers that sample a deserialized input signal at a relatively slow clock speed. Data latency between the input and output signals is controllable to a higher granularity than the input signal with bit positions corresponding to the high-speed input signal. A predictive learning algorithm receives data latency values from the input signal and corresponding data latency values from the output signal to correct and control output latency, potentially within one high speed clock cycle.

Abstract: A system and a method. The system may include a computing device configured for monitoring delay across clock domains using a dynamic phase shift. The computing device may be further configured to: use a counter value of a counter, a known primary clock period of a primary clock domain, a known secondary clock period of a secondary clock domain, and a current phase shift between a secondary clock and a phase shifted secondary clock to calculate a current offset between a last rising edge of the primary clock and a current rising edge of the secondary clock.

Abstract: A system may include a processor configured to: receive ambient data from an environment; calculate an average amplitude of the ambient data as a measure of a noise floor; receive a signal of interest found by the signal exceeding a noise riding threshold, the noise riding floor being an upward offset from the noise floor; calculate a running average for amplitude and frequency of the signal of interest; calculate a running variance for the amplitude and the frequency of the signal of interest; use the running average and the running variance to provide an adjustment to limits for modulation detection; use an offset from the noise riding threshold to provide a signal qualification minimum amplitude; and qualify the signal of interest based at least on the signal qualification minimum amplitude.

Abstract: A system and a method. The system may include a computing device configured for monitoring delay across clock domains using a dynamic phase shift. The computing device may be further configured to: use a counter value of a counter, a known primary clock period of a primary clock domain, a known secondary clock period of a secondary clock domain, and a current phase shift between a secondary clock and a phase shifted secondary clock to calculate a current offset between a last rising edge of the primary clock and a current rising edge of the secondary clock.

Abstract: A system and a method. The system may include a computing device configured for monitoring delay across clock domains using a constant phase shift. The computing device may be further configured to: use a counter value, a known clock period of a primary clock domain, and a known clock period of a secondary clock domain to calculate a current offset between a last rising edge of a primary clock and a current rising edge of a secondary clock; monitor a calibration signal to verify alignment such that a zero state occurs when expected; and adjust a counter to maintain the alignment.

Abstract: A system may include a field-programmable gate array (FPGA). The FPGA may be configured to: determine a time corresponding to in which of x time periods a signal arrived at an input serializer based at least on a value; and determine a time when the signal arrived at an input pad based at least on a shift register latency value and the time corresponding to in which of the x time periods the signal arrived at the input serializer based at least on the value.